// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  peri_cfg_c_union_define.h
// Project line  :  ICT
// Department    :  ICT Processor Chipset Development Dep
// Author        :  Huawei
// Version       :  1.0
// Date          :  2017/11/13
// Description   :  The description of Hi MINI project
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/03/16 18:04:32 Create file
// ******************************************************************************

#ifndef __PERI_CFG_C_UNION_DEFINE_H__
#define __PERI_CFG_C_UNION_DEFINE_H__

/* Define the union U_SC_ITS_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_0      : 31  ; /* [31:1] */
        unsigned int    icg_en_its : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ITS_CLK_EN;

/* Define the union U_SC_ITS_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_1       : 31  ; /* [31:1] */
        unsigned int    icg_dis_its : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ITS_CLK_DIS;

/* Define the union U_SC_FTE_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_2      : 31  ; /* [31:1] */
        unsigned int    icg_en_fte : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_FTE_CLK_EN;

/* Define the union U_SC_FTE_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_3       : 31  ; /* [31:1] */
        unsigned int    icg_dis_fte : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_FTE_CLK_DIS;

/* Define the union U_SC_DBG_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_4      : 31  ; /* [31:1] */
        unsigned int    icg_en_dbg : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_DBG_CLK_EN;

/* Define the union U_SC_DBG_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_5       : 31  ; /* [31:1] */
        unsigned int    icg_dis_dbg : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_DBG_CLK_DIS;

/* Define the union U_SC_M3_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_6     : 31  ; /* [31:1] */
        unsigned int    icg_en_m3 : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_CLK_EN;

/* Define the union U_SC_M3_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_7      : 31  ; /* [31:1] */
        unsigned int    icg_dis_m3 : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_CLK_DIS;

/* Define the union U_SC_GPIO_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_8       : 30  ; /* [31:2] */
        unsigned int    icg_en_gpio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GPIO_CLK_EN;

/* Define the union U_SC_GPIO_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_9        : 30  ; /* [31:2] */
        unsigned int    icg_dis_gpio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GPIO_CLK_DIS;

/* Define the union U_SC_GIC_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_10     : 31  ; /* [31:1] */
        unsigned int    icg_en_gic : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GIC_CLK_EN;

/* Define the union U_SC_GIC_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_11      : 31  ; /* [31:1] */
        unsigned int    icg_dis_gic : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GIC_CLK_DIS;

/* Define the union U_SC_SMMU_ICG_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_12            : 31  ; /* [31:1] */
        unsigned int    icg_en_smmu_trans : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SMMU_ICG_EN;

/* Define the union U_SC_SMMU_ICG_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_13             : 31  ; /* [31:1] */
        unsigned int    icg_dis_smmu_trans : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SMMU_ICG_DIS;

/* Define the union U_SC_TIMER32_CLK_EN0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_14        : 2  ; /* [31:30] */
        unsigned int    icg_en_timer0 : 30  ; /* [29:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER32_CLK_EN0;

/* Define the union U_SC_TIMER32_CLK_DIS0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_15         : 2  ; /* [31:30] */
        unsigned int    icg_dis_timer0 : 30  ; /* [29:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER32_CLK_DIS0;

/* Define the union U_SC_TIMER32_CLK_EN1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    icg_en_timer1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER32_CLK_EN1;

/* Define the union U_SC_TIMER32_CLK_DIS1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    icg_dis_timer1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER32_CLK_DIS1;

/* Define the union U_SC_TIMER64_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    icg_en_timer2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER64_CLK_EN;

/* Define the union U_SC_TIMER64_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    icg_dis_timer2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER64_CLK_DIS;

/* Define the union U_SC_WATCHDOG_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_16      : 21  ; /* [31:11] */
        unsigned int    icg_en_wdog : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_WATCHDOG_CLK_EN;

/* Define the union U_SC_WATCHDOG_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_17       : 21  ; /* [31:11] */
        unsigned int    icg_dis_wdog : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_WATCHDOG_CLK_DIS;

/* Define the union U_SC_UART_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_18      : 28  ; /* [31:4] */
        unsigned int    rsv_19      : 3  ; /* [3:1] */
        unsigned int    icg_en_uart : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_UART_CLK_EN;

/* Define the union U_SC_UART_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_20       : 28  ; /* [31:4] */
        unsigned int    rsv_21       : 3  ; /* [3:1] */
        unsigned int    icg_dis_uart : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_UART_CLK_DIS;

/* Define the union U_SC_MDIO_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_22      : 30  ; /* [31:2] */
        unsigned int    icg_en_mdio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_MDIO_CLK_EN;

/* Define the union U_SC_MDIO_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_23       : 30  ; /* [31:2] */
        unsigned int    icg_dis_mdio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_MDIO_CLK_DIS;

/* Define the union U_SC_SMB_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_24     : 31  ; /* [31:1] */
        unsigned int    icg_en_smb : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SMB_CLK_EN;

/* Define the union U_SC_SMB_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_25      : 31  ; /* [31:1] */
        unsigned int    icg_dis_smb : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SMB_CLK_DIS;

/* Define the union U_SC_CER_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_26       : 30  ; /* [31:2] */
        unsigned int    icg_en_cer_s : 1  ; /* [1] */
        unsigned int    icg_en_cer_m : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CER_CLK_EN;

/* Define the union U_SC_CER_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_27        : 30  ; /* [31:2] */
        unsigned int    icg_dis_cer_s : 1  ; /* [1] */
        unsigned int    icg_dis_cer_m : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CER_CLK_DIS;

/* Define the union U_SC_SFC2X_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_28       : 31  ; /* [31:1] */
        unsigned int    icg_en_sfc2x : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SFC2X_CLK_EN;

/* Define the union U_SC_SC2X_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_29        : 31  ; /* [31:1] */
        unsigned int    icg_dis_sfc2x : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SC2X_CLK_DIS;

/* Define the union U_SC_SFC1X_CLK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_30       : 31  ; /* [31:1] */
        unsigned int    icg_en_sfc1x : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SFC1X_CLK_EN;

/* Define the union U_SC_SFC1X_CLK_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_31        : 31  ; /* [31:1] */
        unsigned int    icg_dis_sfc1x : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SFC1X_CLK_DIS;

/* Define the union U_SC_SDMA_ICG_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_32      : 31  ; /* [31:1] */
        unsigned int    icg_en_sdma : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SDMA_ICG_EN;

/* Define the union U_SC_SDMA_ICG_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_33       : 31  ; /* [31:1] */
        unsigned int    icg_dis_sdma : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SDMA_ICG_DIS;

/* Define the union U_SC_TRNG_ICG_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_34      : 31  ; /* [31:1] */
        unsigned int    icg_en_trng : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TRNG_ICG_EN;

/* Define the union U_SC_TRNG_ICG_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_35       : 31  ; /* [31:1] */
        unsigned int    icg_dis_trng : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TRNG_ICG_DIS;

/* Define the union U_SC_EMMC_ICG_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_36      : 31  ; /* [31:1] */
        unsigned int    icg_en_emmc : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EMMC_ICG_EN;

/* Define the union U_SC_EMMC_ICG_DIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_37       : 31  ; /* [31:1] */
        unsigned int    icg_dis_emmc : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EMMC_ICG_DIS;

/* Define the union U_SC_ITS_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_38       : 31  ; /* [31:1] */
        unsigned int    srst_req_its : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ITS_RESET_REQ;

/* Define the union U_SC_ITS_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_39        : 31  ; /* [31:1] */
        unsigned int    srst_dreq_its : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ITS_RESET_DREQ;

/* Define the union U_SC_FTE_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_40       : 31  ; /* [31:1] */
        unsigned int    srst_req_fte : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_FTE_RESET_REQ;

/* Define the union U_SC_FTE_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_41        : 31  ; /* [31:1] */
        unsigned int    srst_dreq_fte : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_FTE_RESET_DREQ;

/* Define the union U_SC_DBG_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_42       : 31  ; /* [31:1] */
        unsigned int    srst_req_dbg : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_DBG_RESET_REQ;

/* Define the union U_SC_DBG_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_43        : 31  ; /* [31:1] */
        unsigned int    srst_dreq_dbg : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_DBG_RESET_DREQ;

/* Define the union U_SC_GPIO_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_44        : 29  ; /* [31:3] */
        unsigned int    rsv_45        : 1  ; /* [2] */
        unsigned int    srst_req_gpio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GPIO_RESET_REQ;

/* Define the union U_SC_GPIO_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_46         : 29  ; /* [31:3] */
        unsigned int    rsv_47         : 1  ; /* [2] */
        unsigned int    srst_dreq_gpio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GPIO_RESET_DREQ;

/* Define the union U_SC_WATCHDOG_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_48        : 21  ; /* [31:11] */
        unsigned int    srst_req_wdog : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_WATCHDOG_RESET_REQ;

/* Define the union U_SC_WATCHDOG_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_49         : 21  ; /* [31:11] */
        unsigned int    srst_dreq_wdog : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_WATCHDOG_RESET_DREQ;

/* Define the union U_SC_GIC_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_50       : 31  ; /* [31:1] */
        unsigned int    srst_req_gic : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GIC_RESET_REQ;

/* Define the union U_SC_GIC_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_51        : 31  ; /* [31:1] */
        unsigned int    srst_dreq_gic : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GIC_RESET_DREQ;

/* Define the union U_SC_UART_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_52        : 28  ; /* [31:4] */
        unsigned int    rsv_53        : 3  ; /* [3:1] */
        unsigned int    srst_req_uart : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_UART_RESET_REQ;

/* Define the union U_SC_UART_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_54         : 28  ; /* [31:4] */
        unsigned int    rsv_55         : 3  ; /* [3:1] */
        unsigned int    srst_dreq_uart : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_UART_RESET_DREQ;

/* Define the union U_SC_MDIO_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_56        : 30  ; /* [31:2] */
        unsigned int    srst_req_mdio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_MDIO_RESET_REQ;

/* Define the union U_SC_MDIO_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_57         : 30  ; /* [31:2] */
        unsigned int    srst_dreq_mdio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_MDIO_RESET_DREQ;

/* Define the union U_SC_M3_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_58           : 16  ; /* [31:16] */
        unsigned int    srst_req_m3_7    : 1  ; /* [15] */
        unsigned int    srst_req_m3_6    : 1  ; /* [14] */
        unsigned int    srst_req_m3_5    : 1  ; /* [13] */
        unsigned int    srst_req_m3_4    : 1  ; /* [12] */
        unsigned int    srst_req_m3_3    : 1  ; /* [11] */
        unsigned int    srst_req_m3_2    : 1  ; /* [10] */
        unsigned int    srst_req_m3_1    : 1  ; /* [9] */
        unsigned int    srst_req_m3_0    : 1  ; /* [8] */
        unsigned int    srst_req_m3_por7 : 1  ; /* [7] */
        unsigned int    srst_req_m3_por6 : 1  ; /* [6] */
        unsigned int    srst_req_m3_por5 : 1  ; /* [5] */
        unsigned int    srst_req_m3_por4 : 1  ; /* [4] */
        unsigned int    srst_req_m3_por3 : 1  ; /* [3] */
        unsigned int    srst_req_m3_por2 : 1  ; /* [2] */
        unsigned int    srst_req_m3_por1 : 1  ; /* [1] */
        unsigned int    srst_req_m3_por0 : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_RESET_REQ;

/* Define the union U_SC_M3_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_59            : 16  ; /* [31:16] */
        unsigned int    srst_dreq_m3_7    : 1  ; /* [15] */
        unsigned int    srst_dreq_m3_6    : 1  ; /* [14] */
        unsigned int    srst_dreq_m3_5    : 1  ; /* [13] */
        unsigned int    srst_dreq_m3_4    : 1  ; /* [12] */
        unsigned int    srst_dreq_m3_3    : 1  ; /* [11] */
        unsigned int    srst_dreq_m3_2    : 1  ; /* [10] */
        unsigned int    srst_dreq_m3_1    : 1  ; /* [9] */
        unsigned int    srst_dreq_m3_0    : 1  ; /* [8] */
        unsigned int    srst_dreq_m3_por7 : 1  ; /* [7] */
        unsigned int    srst_dreq_m3_por6 : 1  ; /* [6] */
        unsigned int    srst_dreq_m3_por5 : 1  ; /* [5] */
        unsigned int    srst_dreq_m3_por4 : 1  ; /* [4] */
        unsigned int    srst_dreq_m3_por3 : 1  ; /* [3] */
        unsigned int    srst_dreq_m3_por2 : 1  ; /* [2] */
        unsigned int    srst_dreq_m3_por1 : 1  ; /* [1] */
        unsigned int    srst_dreq_m3_por0 : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_RESET_DREQ;

/* Define the union U_SC_SMB_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_60       : 31  ; /* [31:1] */
        unsigned int    srst_req_smb : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SMB_RESET_REQ;

/* Define the union U_SC_SMB_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_61        : 31  ; /* [31:1] */
        unsigned int    srst_dreq_smb : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SMB_RESET_DREQ;

/* Define the union U_SC_CER_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_62         : 30  ; /* [31:2] */
        unsigned int    srst_req_cer_s : 1  ; /* [1] */
        unsigned int    srst_req_cer_m : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CER_RESET_REQ;

/* Define the union U_SC_CER_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_63          : 30  ; /* [31:2] */
        unsigned int    srst_dreq_cer_s : 1  ; /* [1] */
        unsigned int    srst_dreq_cer_m : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CER_RESET_DREQ;

/* Define the union U_SC_TIMER_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_64         : 2  ; /* [31:30] */
        unsigned int    srst_req_timer : 30  ; /* [29:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER_RESET_REQ;

/* Define the union U_SC_TIMER_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_65          : 2  ; /* [31:30] */
        unsigned int    srst_dreq_timer : 30  ; /* [29:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER_RESET_DREQ;

/* Define the union U_SC_SFC_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_66           : 29  ; /* [31:3] */
        unsigned int    srst_req_sfc_bus : 1  ; /* [2] */
        unsigned int    srst_req_sfc2x   : 1  ; /* [1] */
        unsigned int    srst_req_sfc1x   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SFC_RESET_REQ;

/* Define the union U_SC_SFC_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_67            : 29  ; /* [31:3] */
        unsigned int    srst_dreq_sfc_bus : 1  ; /* [2] */
        unsigned int    srst_dreq_sfc2x   : 1  ; /* [1] */
        unsigned int    srst_dreq_sfc1x   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SFC_RESET_DREQ;

/* Define the union U_SC_SDMA_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_68        : 31  ; /* [31:1] */
        unsigned int    srst_req_sdma : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SDMA_RESET_REQ;

/* Define the union U_SC_SDMA_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_69         : 31  ; /* [31:1] */
        unsigned int    srst_dreq_sdma : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SDMA_RESET_DREQ;

/* Define the union U_SC_TRNG_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_70        : 31  ; /* [31:1] */
        unsigned int    srst_req_trng : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TRNG_RESET_REQ;

/* Define the union U_SC_TRNG_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_71         : 31  ; /* [31:1] */
        unsigned int    srst_dreq_trng : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TRNG_RESET_DREQ;

/* Define the union U_SC_EMMC_RESET_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_72        : 31  ; /* [31:1] */
        unsigned int    srst_req_emmc : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EMMC_RESET_REQ;

/* Define the union U_SC_EMMC_RESET_DREQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_73         : 31  ; /* [31:1] */
        unsigned int    srst_dreq_emmc : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EMMC_RESET_DREQ;

/* Define the union U_SC_CHAIN_ERR_CLR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_74        : 31  ; /* [31:1] */
        unsigned int    chain_err_int : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CHAIN_ERR_CLR;

/* Define the union U_SC_CHAIN_ERR_INTMASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_75            : 31  ; /* [31:1] */
        unsigned int    chain_err_intmask : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CHAIN_ERR_INTMASK;

/* Define the union U_SC_CHAIN_ERR_INT_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_76              : 31  ; /* [31:1] */
        unsigned int    chain_err_intstatus : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CHAIN_ERR_INT_STATUS;

/* Define the union U_SC_CHAIN_ERR_CPU_CLR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_77            : 31  ; /* [31:1] */
        unsigned int    chain_err_cpu_int : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CHAIN_ERR_CPU_CLR;

/* Define the union U_SC_CHAIN_ERR_CPU_INTMASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_78                : 31  ; /* [31:1] */
        unsigned int    chain_err_cpu_intmask : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CHAIN_ERR_CPU_INTMASK;

/* Define the union U_SC_CHAIN_ERR_CPU_INT_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_79                  : 31  ; /* [31:1] */
        unsigned int    chain_err_cpu_intstatus : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CHAIN_ERR_CPU_INT_STATUS;

/* Define the union U_SC_DISPATCH_ERRRSP */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_80         : 31  ; /* [31:1] */
        unsigned int    errrsp_disable : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_DISPATCH_ERRRSP;

/* Define the union U_SC_M3_CTRL0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_81     : 1  ; /* [31] */
        unsigned int    m3_dbgen   : 1  ; /* [30] */
        unsigned int    rsv_82     : 1  ; /* [29] */
        unsigned int    rsv_83     : 1  ; /* [28] */
        unsigned int    m3_rxev    : 1  ; /* [27] */
        unsigned int    m3_intnmi  : 1  ; /* [26] */
        unsigned int    m3_stcalib : 26  ; /* [25:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_CTRL0;

/* Define the union U_SC_M3_CTRL1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_84          : 6  ; /* [31:26] */
        unsigned int    m3_niden        : 1  ; /* [25] */
        unsigned int    m3_dapen        : 1  ; /* [24] */
        unsigned int    m3_bootrom_addr : 24  ; /* [23:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_CTRL1;

/* Define the union U_SC_TSENSOR1_ALARM0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_85              : 2  ; /* [31:30] */
        unsigned int    tsensor1_ultra_high : 10  ; /* [29:20] */
        unsigned int    tsensor1_high       : 10  ; /* [19:10] */
        unsigned int    tsensor1_low        : 10  ; /* [9:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TSENSOR1_ALARM0;

/* Define the union U_SC_TSENSOR1_SAMPLE_NUM */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_86                    : 28  ; /* [31:4] */
        unsigned int    tsensor1_sample_shift_num : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TSENSOR1_SAMPLE_NUM;

/* Define the union U_SC_TSENSOR1_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_87               : 18  ; /* [31:14] */
        unsigned int    tsensor1_temp_ct_sel : 2  ; /* [13:12] */
        unsigned int    rsv_88               : 10  ; /* [11:2] */
        unsigned int    tsensor1_temp_calib  : 1  ; /* [1] */
        unsigned int    tsensor1_temp_en     : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TSENSOR1_CTRL;

/* Define the union U_SC_ULTRASOC_USER_CFG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_89            : 26  ; /* [31:6] */
        unsigned int    axi_user_ultrasoc : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ULTRASOC_USER_CFG;

/* Define the union U_SC_ULTRASOC_PORT_SEL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_90           : 31  ; /* [31:1] */
        unsigned int    ultrasoc_msg_sel : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ULTRASOC_PORT_SEL;

/* Define the union U_SC_ULTRASOC_USER_NS_CFG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_91               : 31  ; /* [31:1] */
        unsigned int    axi_user_ns_ultrasoc : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ULTRASOC_USER_NS_CFG;

/* Define the union U_SC_ULTRASOC_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_92         : 26  ; /* [31:6] */
        unsigned int    wtsel_etf      : 2  ; /* [5:4] */
        unsigned int    rtsel_etf      : 2  ; /* [3:2] */
        unsigned int    ultrasoc_niden : 1  ; /* [1] */
        unsigned int    ultrasoc_dbgen : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ULTRASOC_CTRL;

/* Define the union U_SC_M3_REMAP_ADDR_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_93           : 16  ; /* [31:16] */
        unsigned int    m3_remap_addr_en : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_EN;

/* Define the union U_SC_M3_REMAP_ADDR_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_94          : 20  ; /* [31:12] */
        unsigned int    m3_remap_addr_0 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_0;

/* Define the union U_SC_M3_REMAP_ADDR_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_95          : 16  ; /* [31:16] */
        unsigned int    m3_remap_addr_1 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_1;

/* Define the union U_SC_M3_REMAP_ADDR_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_96          : 20  ; /* [31:12] */
        unsigned int    m3_remap_addr_2 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_2;

/* Define the union U_SC_M3_REMAP_ADDR_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_97          : 20  ; /* [31:12] */
        unsigned int    m3_remap_addr_3 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_3;

/* Define the union U_SC_M3_REMAP_ADDR_4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_98          : 20  ; /* [31:12] */
        unsigned int    m3_remap_addr_4 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_4;

/* Define the union U_SC_M3_REMAP_ADDR_5 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_99          : 20  ; /* [31:12] */
        unsigned int    m3_remap_addr_5 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_5;

/* Define the union U_SC_M3_REMAP_ADDR_6 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_100         : 20  ; /* [31:12] */
        unsigned int    m3_remap_addr_6 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_6;

/* Define the union U_SC_M3_REMAP_ADDR_7 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_101         : 20  ; /* [31:12] */
        unsigned int    m3_remap_addr_7 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_7;

/* Define the union U_SC_M3_REMAP_ADDR_8 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_102         : 16  ; /* [31:16] */
        unsigned int    rsv_103         : 4  ; /* [15:12] */
        unsigned int    m3_remap_addr_8 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_8;

/* Define the union U_SC_M3_REMAP_ADDR_9 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_104         : 16  ; /* [31:16] */
        unsigned int    rsv_105         : 4  ; /* [15:12] */
        unsigned int    m3_remap_addr_9 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_9;

/* Define the union U_SC_M3_REMAP_ADDR_10 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_106          : 16  ; /* [31:16] */
        unsigned int    rsv_107          : 4  ; /* [15:12] */
        unsigned int    m3_remap_addr_10 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_10;

/* Define the union U_SC_M3_REMAP_ADDR_11 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_108          : 16  ; /* [31:16] */
        unsigned int    rsv_109          : 4  ; /* [15:12] */
        unsigned int    m3_remap_addr_11 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_11;

/* Define the union U_SC_M3_REMAP_ADDR_12 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_110          : 16  ; /* [31:16] */
        unsigned int    rsv_111          : 4  ; /* [15:12] */
        unsigned int    m3_remap_addr_12 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_12;

/* Define the union U_SC_M3_REMAP_ADDR_13 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_112          : 16  ; /* [31:16] */
        unsigned int    rsv_113          : 4  ; /* [15:12] */
        unsigned int    m3_remap_addr_13 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_13;

/* Define the union U_SC_M3_REMAP_ADDR_14 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_114          : 16  ; /* [31:16] */
        unsigned int    rsv_115          : 4  ; /* [15:12] */
        unsigned int    m3_remap_addr_14 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_14;

/* Define the union U_SC_M3_REMAP_ADDR_15 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_116          : 16  ; /* [31:16] */
        unsigned int    rsv_117          : 4  ; /* [15:12] */
        unsigned int    m3_remap_addr_15 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_REMAP_ADDR_15;

/* Define the union U_SC_CFG_AXUSER_L_M3_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sc_cfg_axuser_l_m3_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_AXUSER_L_M3_0;

/* Define the union U_SC_CFG_AXUSER_M_M3_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sc_cfg_axuser_m_m3_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_AXUSER_M_M3_0;

/* Define the union U_SC_CFG_AXUSER_H_M3_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_118              : 28  ; /* [31:4] */
        unsigned int    sc_cfg_axuser_h_m3_0 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_AXUSER_H_M3_0;

/* Define the union U_SC_CFG_CACHE_CTRL_M3_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_119             : 28  ; /* [31:4] */
        unsigned int    sc_cfg_axcache_m3_0 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_CACHE_CTRL_M3_0;

/* Define the union U_SC_CFG_AXUSER_L_M3_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sc_cfg_axuser_l_m3_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_AXUSER_L_M3_1;

/* Define the union U_SC_CFG_AXUSER_M_M3_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sc_cfg_axuser_m_m3_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_AXUSER_M_M3_1;

/* Define the union U_SC_CFG_AXUSER_H_M3_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_120              : 28  ; /* [31:4] */
        unsigned int    sc_cfg_axuser_h_m3_1 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_AXUSER_H_M3_1;

/* Define the union U_SC_CFG_CACHE_CTRL_M3_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_121             : 28  ; /* [31:4] */
        unsigned int    sc_cfg_axcache_m3_1 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_CACHE_CTRL_M3_1;

/* Define the union U_SC_CFG_AXUSER_L_M3_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sc_cfg_axuser_l_m3_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_AXUSER_L_M3_2;

/* Define the union U_SC_CFG_AXUSER_M_M3_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sc_cfg_axuser_m_m3_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_AXUSER_M_M3_2;

/* Define the union U_SC_CFG_AXUSER_H_M3_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_122              : 28  ; /* [31:4] */
        unsigned int    sc_cfg_axuser_h_m3_2 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_AXUSER_H_M3_2;

/* Define the union U_SC_CFG_CACHE_CTRL_M3_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_123             : 28  ; /* [31:4] */
        unsigned int    sc_cfg_axcache_m3_2 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_CACHE_CTRL_M3_2;

/* Define the union U_SC_QOS_CTRL_M3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_124     : 24  ; /* [31:8] */
        unsigned int    sc_arqos_m3 : 4  ; /* [7:4] */
        unsigned int    sc_awqos_m3 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_QOS_CTRL_M3;

/* Define the union U_SC_QOS_CTRL_GIC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_125      : 24  ; /* [31:8] */
        unsigned int    sc_arqos_gic : 4  ; /* [7:4] */
        unsigned int    sc_awqos_gic : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_QOS_CTRL_GIC;

/* Define the union U_SC_QOS_CTRL_EMMC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_126       : 24  ; /* [31:8] */
        unsigned int    sc_arqos_emmc : 4  ; /* [7:4] */
        unsigned int    sc_awqos_emmc : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_QOS_CTRL_EMMC;

/* Define the union U_SC_QOS_CTRL_SDMAM */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_127        : 24  ; /* [31:8] */
        unsigned int    sc_arqos_sdmam : 4  ; /* [7:4] */
        unsigned int    sc_awqos_sdmam : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_QOS_CTRL_SDMAM;

/* Define the union U_SC_EXT_INT_POLARITY */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_128                  : 18  ; /* [31:14] */
        unsigned int    sc_m2_perst_int_polarity : 1  ; /* [13] */
        unsigned int    sc_ge_phy_int_polarity   : 1  ; /* [12] */
        unsigned int    sc_gphy_int_polarity     : 1  ; /* [11] */
        unsigned int    sc_pmu_int_polarity      : 2  ; /* [10:9] */
        unsigned int    sc_ext_int_polarity      : 9  ; /* [8:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EXT_INT_POLARITY;

/* Define the union U_SC_CFG_BUS_CTRL0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_129                : 31  ; /* [31:1] */
        unsigned int    sc_cmd_delay_en_cfgbus : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_BUS_CTRL0;

/* Define the union U_SC_CFG_BUS_CTRL1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sc_counter_cmd_delay_cfgbus : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_BUS_CTRL1;

/* Define the union U_SC_CFG_BUS_DBG_CTRL0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_130                    : 31  ; /* [31:1] */
        unsigned int    sc_cmd_delay_en_cfgbus_dbg : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_BUS_DBG_CTRL0;

/* Define the union U_SC_CFG_BUS_DBG_CTRL1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sc_counter_cmd_delay_cfgbus_dbg : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_BUS_DBG_CTRL1;

/* Define the union U_SC_MEM_CTRL_SMMU */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_131             : 19  ; /* [31:13] */
        unsigned int    mem_power_mode_smmu : 6  ; /* [12:7] */
        unsigned int    sp_ram_tmod_smmu    : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_MEM_CTRL_SMMU;

/* Define the union U_SC_MEM_CTRL_GIC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_132         : 25  ; /* [31:7] */
        unsigned int    sp_ram_tmod_gic : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_MEM_CTRL_GIC;

/* Define the union U_SC_MEM_CTRL_ULTRASOC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_133              : 25  ; /* [31:7] */
        unsigned int    sp_ram_tmod_ultrasoc : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_MEM_CTRL_ULTRASOC;

/* Define the union U_SC_MEM_CTRL_CER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_134            : 19  ; /* [31:13] */
        unsigned int    mem_power_mode_cer : 6  ; /* [12:7] */
        unsigned int    sp_ram_tmod_cer    : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_MEM_CTRL_CER;

/* Define the union U_SC_MEM_CTRL_TRNG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_135             : 19  ; /* [31:13] */
        unsigned int    mem_power_mode_trng : 6  ; /* [12:7] */
        unsigned int    sp_ram_tmod_trng    : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_MEM_CTRL_TRNG;

/* Define the union U_SC_TIMER64_EN_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_136            : 22  ; /* [31:10] */
        unsigned int    timer64_en_externa : 10  ; /* [9:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER64_EN_CTRL;

/* Define the union U_SC_WDOG_SRST_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    crg_srst_wdog_en : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_WDOG_SRST_MASK;

/* Define the union U_SC_TIMER_CLK_SEL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_137       : 30  ; /* [31:2] */
        unsigned int    timer_clk_sel : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER_CLK_SEL;

/* Define the union U_SC_BUS_NUM_PERI */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_138    : 24  ; /* [31:8] */
        unsigned int    sc_bus_num : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_BUS_NUM_PERI;

/* Define the union U_SC_DVE_NUM_PERI */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_139    : 24  ; /* [31:8] */
        unsigned int    sc_dev_num : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_DVE_NUM_PERI;

/* Define the union U_SC_CFG_BUS_WAIT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_140           : 12  ; /* [31:20] */
        unsigned int    rd_wait_cycle     : 10  ; /* [19:10] */
        unsigned int    rd_wait_cycle_cpu : 10  ; /* [9:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CFG_BUS_WAIT;

/* Define the union U_SC_EMMC_CLK_SEL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_141      : 31  ; /* [31:1] */
        unsigned int    emmc_clk_sel : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EMMC_CLK_SEL;

/* Define the union U_SC_AXI_USER_L32_EMMC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sc_axi_user_l32_emmc : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_AXI_USER_L32_EMMC;

/* Define the union U_SC_AXI_USER_H32_EMMC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sc_axi_user_h32_emmc : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_AXI_USER_H32_EMMC;

/* Define the union U_SC_AXI_USER_67_64_EMMC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_142                 : 28  ; /* [31:4] */
        unsigned int    sc_axi_user_h67_64_emmc : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_AXI_USER_67_64_EMMC;

/* Define the union U_SC_AXI_CACHE_EMMC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_143           : 28  ; /* [31:4] */
        unsigned int    sc_axi_cache_emmc : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_AXI_CACHE_EMMC;

/* Define the union U_SC_AXI_PORT_SEL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_144         : 31  ; /* [31:1] */
        unsigned int    sc_axi_port_sel : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_AXI_PORT_SEL;

/* Define the union U_SC_SFC_BYP_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_145           : 30  ; /* [31:2] */
        unsigned int    sc_byp_en_sfc_mem : 1  ; /* [1] */
        unsigned int    sc_byp_en_sfc_reg : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SFC_BYP_CTRL;

/* Define the union U_SC_AHB_BYP_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_146       : 30  ; /* [31:2] */
        unsigned int    sc_byp_en_smb : 1  ; /* [1] */
        unsigned int    sc_byp_en_cer : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_AHB_BYP_CTRL;

/* Define the union U_SC_UART_SEL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_147     : 29  ; /* [31:3] */
        unsigned int    sc_uart_sel : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_UART_SEL;

/* Define the union U_SC_ULTRASOC_USER_CRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_148             : 24  ; /* [31:8] */
        unsigned int    sc_axqos_ultrasoc   : 4  ; /* [7:4] */
        unsigned int    sc_axcache_ultrasoc : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ULTRASOC_USER_CRL;

/* Define the union U_SC_ULTRASOC_AXPROT_CRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_149            : 26  ; /* [31:6] */
        unsigned int    sc_arprot_ultrasoc : 3  ; /* [5:3] */
        unsigned int    sc_awprot_ultrasoc : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ULTRASOC_AXPROT_CRL;

/* Define the union U_SC_SFC_DAW_CRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_150     : 6  ; /* [31:26] */
        unsigned int    sc_daw_en   : 1  ; /* [25] */
        unsigned int    sc_daw_size : 5  ; /* [24:20] */
        unsigned int    rsv_151     : 8  ; /* [19:12] */
        unsigned int    sc_daw_addr : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SFC_DAW_CRL;

/* Define the union U_SC_EMMC_HADDR39_CRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_152              : 31  ; /* [31:1] */
        unsigned int    sc_ahb_haddr_39_emmc : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EMMC_HADDR39_CRL;

/* Define the union U_SC_EXT_INT_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_153      : 18  ; /* [31:14] */
        unsigned int    ext_int_mask : 14  ; /* [13:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EXT_INT_MASK;

/* Define the union U_SC_AO_WAKEUP_INT_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_154          : 29  ; /* [31:3] */
        unsigned int    hipcie_int_mask  : 1  ; /* [2] */
        unsigned int    timer64_int_mask : 1  ; /* [1] */
        unsigned int    gpio0_int_mask   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_AO_WAKEUP_INT_MASK;

/* Define the union U_SC_TSENSOR1_INT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_155             : 29  ; /* [31:3] */
        unsigned int    tsensor1_ultra_over : 1  ; /* [2] */
        unsigned int    tsensor1_over       : 1  ; /* [1] */
        unsigned int    tsensor1_under      : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TSENSOR1_INT;

/* Define the union U_SC_TSENSOR1_INT_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_156                      : 29  ; /* [31:3] */
        unsigned int    tsensor1_ultra_over_int_mask : 1  ; /* [2] */
        unsigned int    tsensor1_over_int_mask       : 1  ; /* [1] */
        unsigned int    tsensor1_under_int_mask      : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TSENSOR1_INT_MASK;

/* Define the union U_SC_PCIE_PERST_INT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_157    : 31  ; /* [31:1] */
        unsigned int    pcie_perst : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_PCIE_PERST_INT;

/* Define the union U_SC_PCIE_PERST_INT_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_158             : 31  ; /* [31:1] */
        unsigned int    pcie_perst_int_mask : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_PCIE_PERST_INT_MASK;

/* Define the union U_SC_PWR_CORE_INT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_159  : 24  ; /* [31:8] */
        unsigned int    pwr_core : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_PWR_CORE_INT;

/* Define the union U_SC_PWR_CORE_INT_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_160           : 24  ; /* [31:8] */
        unsigned int    pwr_core_int_mask : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_PWR_CORE_INT_MASK;

/* Define the union U_SC_ITS_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_161    : 31  ; /* [31:1] */
        unsigned int    icg_st_its : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ITS_CLK_ST;

/* Define the union U_SC_FTE_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_162    : 31  ; /* [31:1] */
        unsigned int    icg_st_fte : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_FTE_CLK_ST;

/* Define the union U_SC_DBG_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_163    : 31  ; /* [31:1] */
        unsigned int    icg_st_dbg : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_DBG_CLK_ST;

/* Define the union U_SC_M3_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_164   : 31  ; /* [31:1] */
        unsigned int    icg_st_m3 : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_CLK_ST;

/* Define the union U_SC_GPIO_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_165     : 30  ; /* [31:2] */
        unsigned int    icg_st_gpio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GPIO_CLK_ST;

/* Define the union U_SC_GIC_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_166    : 31  ; /* [31:1] */
        unsigned int    icg_st_gic : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GIC_CLK_ST;

/* Define the union U_SC_SMMU_ICG_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_167           : 31  ; /* [31:1] */
        unsigned int    icg_st_smmu_trans : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SMMU_ICG_ST;

/* Define the union U_SC_TIMER32_CLK_ST0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_168       : 2  ; /* [31:30] */
        unsigned int    icg_st_timer0 : 30  ; /* [29:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER32_CLK_ST0;

/* Define the union U_SC_TIMER32_CLK_ST1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    icg_st_timer1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER32_CLK_ST1;

/* Define the union U_SC_TIMER64_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    icg_st_timer2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER64_CLK_ST;

/* Define the union U_SC_WATCHDOG_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_169     : 21  ; /* [31:11] */
        unsigned int    icg_st_wdog : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_WATCHDOG_CLK_ST;

/* Define the union U_SC_UART_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_170     : 28  ; /* [31:4] */
        unsigned int    rsv_171     : 3  ; /* [3:1] */
        unsigned int    icg_st_uart : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_UART_CLK_ST;

/* Define the union U_SC_MDIO_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_172     : 30  ; /* [31:2] */
        unsigned int    icg_st_mdio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_MDIO_CLK_ST;

/* Define the union U_SC_SMB_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_173    : 31  ; /* [31:1] */
        unsigned int    icg_st_smb : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SMB_CLK_ST;

/* Define the union U_SC_CER_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_174      : 30  ; /* [31:2] */
        unsigned int    icg_st_cer_s : 1  ; /* [1] */
        unsigned int    icg_st_cer_m : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CER_CLK_ST;

/* Define the union U_SC_SFC2X_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_175      : 31  ; /* [31:1] */
        unsigned int    icg_st_sfc2x : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SFC2X_CLK_ST;

/* Define the union U_SC_SFC1X_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_176      : 31  ; /* [31:1] */
        unsigned int    icg_st_sfc1x : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SFC1X_CLK_ST;

/* Define the union U_SC_SDMA_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_177     : 31  ; /* [31:1] */
        unsigned int    icg_st_sdma : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SDMA_CLK_ST;

/* Define the union U_SC_TRNG_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_178     : 31  ; /* [31:1] */
        unsigned int    icg_st_trng : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TRNG_CLK_ST;

/* Define the union U_SC_EMMC_CLK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_179     : 31  ; /* [31:1] */
        unsigned int    icg_st_emmc : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EMMC_CLK_ST;

/* Define the union U_SC_ITS_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_180     : 31  ; /* [31:1] */
        unsigned int    srst_st_its : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ITS_RESET_ST;

/* Define the union U_SC_FTE_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_181     : 31  ; /* [31:1] */
        unsigned int    srst_st_fte : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_FTE_RESET_ST;

/* Define the union U_SC_DBG_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_182     : 31  ; /* [31:1] */
        unsigned int    srst_st_dbg : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_DBG_RESET_ST;

/* Define the union U_SC_GPIO_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_183      : 29  ; /* [31:3] */
        unsigned int    rsv_184      : 1  ; /* [2] */
        unsigned int    srst_st_gpio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GPIO_RESET_ST;

/* Define the union U_SC_WATCHDOG_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_185      : 21  ; /* [31:11] */
        unsigned int    srst_st_wdog : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_WATCHDOG_RESET_ST;

/* Define the union U_SC_GIC_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_186     : 31  ; /* [31:1] */
        unsigned int    srst_st_gic : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_GIC_RESET_ST;

/* Define the union U_SC_UART_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_187      : 28  ; /* [31:4] */
        unsigned int    rsv_188      : 3  ; /* [3:1] */
        unsigned int    srst_st_uart : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_UART_RESET_ST;

/* Define the union U_SC_MDIO_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_189      : 30  ; /* [31:2] */
        unsigned int    srst_st_mdio : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_MDIO_RESET_ST;

/* Define the union U_SC_M3_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_190         : 16  ; /* [31:16] */
        unsigned int    srst_st_m3_7    : 1  ; /* [15] */
        unsigned int    srst_st_m3_6    : 1  ; /* [14] */
        unsigned int    srst_st_m3_5    : 1  ; /* [13] */
        unsigned int    srst_st_m3_4    : 1  ; /* [12] */
        unsigned int    srst_st_m3_3    : 1  ; /* [11] */
        unsigned int    srst_st_m3_2    : 1  ; /* [10] */
        unsigned int    srst_st_m3_1    : 1  ; /* [9] */
        unsigned int    srst_st_m3_0    : 1  ; /* [8] */
        unsigned int    srst_st_m3_por7 : 1  ; /* [7] */
        unsigned int    srst_st_m3_por6 : 1  ; /* [6] */
        unsigned int    srst_st_m3_por5 : 1  ; /* [5] */
        unsigned int    srst_st_m3_por4 : 1  ; /* [4] */
        unsigned int    srst_st_m3_por3 : 1  ; /* [3] */
        unsigned int    srst_st_m3_por2 : 1  ; /* [2] */
        unsigned int    srst_st_m3_por1 : 1  ; /* [1] */
        unsigned int    srst_st_m3_por0 : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_RESET_ST;

/* Define the union U_SC_SMB_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_191     : 31  ; /* [31:1] */
        unsigned int    srst_st_smb : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SMB_RESET_ST;

/* Define the union U_SC_CER_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_192       : 30  ; /* [31:2] */
        unsigned int    srst_st_cer_s : 1  ; /* [1] */
        unsigned int    srst_st_cer_m : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_CER_RESET_ST;

/* Define the union U_SC_TIMER_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_193       : 2  ; /* [31:30] */
        unsigned int    srsr_st_timer : 30  ; /* [29:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TIMER_RESET_ST;

/* Define the union U_SC_SFC_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_194         : 29  ; /* [31:3] */
        unsigned int    srst_st_sfc_bus : 1  ; /* [2] */
        unsigned int    srst_st_sfc2x   : 1  ; /* [1] */
        unsigned int    srst_st_sfc1x   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SFC_RESET_ST;

/* Define the union U_SC_SDMA_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_195      : 31  ; /* [31:1] */
        unsigned int    srst_st_sdma : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SDMA_RESET_ST;

/* Define the union U_SC_TRNG_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_196      : 31  ; /* [31:1] */
        unsigned int    srst_st_trng : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TRNG_RESET_ST;

/* Define the union U_SC_EMMC_RESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_197      : 31  ; /* [31:1] */
        unsigned int    srst_st_emmc : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EMMC_RESET_ST;

/* Define the union U_SC_TSENSOR1_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_198             : 19  ; /* [31:13] */
        unsigned int    tsensor1_temp_ready : 1  ; /* [12] */
        unsigned int    rsv_199             : 2  ; /* [11:10] */
        unsigned int    tsensor1_temp_out   : 10  ; /* [9:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TSENSOR1_ST;

/* Define the union U_SC_TSENSOR1_TEMP_SAMPLE_AVERAGE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    tsensor1_valid  : 1  ; /* [31] */
        unsigned int    rsv_200         : 21  ; /* [30:10] */
        unsigned int    tsensor1_sample : 10  ; /* [9:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TSENSOR1_TEMP_SAMPLE_AVERAGE;

/* Define the union U_SC_ULTRASOC_MEM_ECC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_201                 : 28  ; /* [31:4] */
        unsigned int    mem_ecc_status_ultrasoc : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ULTRASOC_MEM_ECC;

/* Define the union U_SC_M3_STAT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_202     : 15  ; /* [31:17] */
        unsigned int    rsv_203     : 1  ; /* [16] */
        unsigned int    rsv_204     : 1  ; /* [15] */
        unsigned int    m3_currpri  : 8  ; /* [14:7] */
        unsigned int    m3_sleeping : 1  ; /* [6] */
        unsigned int    m3_lockup   : 1  ; /* [5] */
        unsigned int    m3_halted   : 1  ; /* [4] */
        unsigned int    rsv_205     : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_M3_STAT;

/* Define the union U_SC_PCIE_PERESET_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_206                : 31  ; /* [31:1] */
        unsigned int    pcie_perst_status_soft : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_PCIE_PERESET_ST;

/* Define the union U_SC_EXT_INT_POLARITY_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_207             : 18  ; /* [31:14] */
        unsigned int    ext_int_polarity_st : 14  ; /* [13:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EXT_INT_POLARITY_ST;

/* Define the union U_SC_EXT_INT_POLARITY_MASK_ST */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_208                  : 18  ; /* [31:14] */
        unsigned int    ext_int_polarity_mask_st : 14  ; /* [13:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_EXT_INT_POLARITY_MASK_ST;

/* Define the union U_SC_TRNG_FSM_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_209          : 22  ; /* [31:10] */
        unsigned int    trng_fsm_state   : 3  ; /* [9:7] */
        unsigned int    trng_pproc_state : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TRNG_FSM_CTRL;

/* Define the union U_SC_TSENSOR1_INT_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_210                        : 29  ; /* [31:3] */
        unsigned int    tsensor1_ultra_over_int_status : 1  ; /* [2] */
        unsigned int    tsensor1_over_int_status       : 1  ; /* [1] */
        unsigned int    tsensor1_under_int_status      : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_TSENSOR1_INT_STATUS;

/* Define the union U_SC_PCIE_PERST_INT_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_211               : 31  ; /* [31:1] */
        unsigned int    pcie_perst_int_status : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_PCIE_PERST_INT_STATUS;

/* Define the union U_SC_PWR_CORE_INT_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_212             : 24  ; /* [31:8] */
        unsigned int    pwr_core_int_status : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_PWR_CORE_INT_STATUS;

/* Define the union U_SC_KEY_INFO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_213    : 19  ; /* [31:13] */
        unsigned int    tsc_sync   : 1  ; /* [12] */
        unsigned int    boot_sel1  : 1  ; /* [11] */
        unsigned int    boot_sel0  : 1  ; /* [10] */
        unsigned int    iodie_type : 1  ; /* [9] */
        unsigned int    test_mode1 : 1  ; /* [8] */
        unsigned int    test_mode0 : 1  ; /* [7] */
        unsigned int    mpcore_sel : 1  ; /* [6] */
        unsigned int    rst_mode   : 1  ; /* [5] */
        unsigned int    probe_mode : 1  ; /* [4] */
        unsigned int    die_id     : 2  ; /* [3:2] */
        unsigned int    socket_id  : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_KEY_INFO;

/* Define the union U_PERI_CFG_VERSION0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    peri_cfg_version0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PERI_CFG_VERSION0;

/* Define the union U_PERI_CFG_MAGIC_WORD */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    peri_cfg_magic_word : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PERI_CFG_MAGIC_WORD;

/* Define the union U_PERI_CFG_ECO_CFG0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    peri_cfg_eco_cfg0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PERI_CFG_ECO_CFG0;

/* Define the union U_PERI_CFG_ECO_CFG1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    peri_cfg_eco_cfg1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PERI_CFG_ECO_CFG1;

/* Define the union U_PERI_CFG_ECO_CFG2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    peri_cfg_eco_cfg2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PERI_CFG_ECO_CFG2;

/* Define the union U_PERI_CFG_ECO_CFG3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    peri_cfg_eco_cfg3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PERI_CFG_ECO_CFG3;

/* Define the union U_SC_SYSCTRL_LOCK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sysctrl_lock : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SYSCTRL_LOCK;

/* Define the union U_SC_SYSCTRL_UNLOCK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sysctrl_unlock : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_SYSCTRL_UNLOCK;

/* Define the union U_SC_ECO_RSV0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    eco_rsv0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ECO_RSV0;

/* Define the union U_SC_ECO_RSV1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    eco_rsv1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ECO_RSV1;

/* Define the union U_SC_ECO_RSV2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    eco_rsv2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ECO_RSV2;

/* Define the union U_SC_ECO_RSV3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    eco_rsv3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ECO_RSV3;

/* Define the union U_SC_ECO_RSV4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    prototype_clk : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ECO_RSV4;

/* Define the union U_SC_ECO_RSV5 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    prototype_rst_n : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SC_ECO_RSV5;

/* Define the union U_FPGA_VER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    fpga_veri_num : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_FPGA_VER;


//==============================================================================
/* Define the global struct */
typedef struct
{
    volatile U_SC_ITS_CLK_EN                   SC_ITS_CLK_EN                   ; /* 300 */
    volatile U_SC_ITS_CLK_DIS                  SC_ITS_CLK_DIS                  ; /* 304 */
    volatile U_SC_FTE_CLK_EN                   SC_FTE_CLK_EN                   ; /* 308 */
    volatile U_SC_FTE_CLK_DIS                  SC_FTE_CLK_DIS                  ; /* 30C */
    volatile U_SC_DBG_CLK_EN                   SC_DBG_CLK_EN                   ; /* 310 */
    volatile U_SC_DBG_CLK_DIS                  SC_DBG_CLK_DIS                  ; /* 314 */
    volatile U_SC_M3_CLK_EN                    SC_M3_CLK_EN                    ; /* 318 */
    volatile U_SC_M3_CLK_DIS                   SC_M3_CLK_DIS                   ; /* 31C */
    volatile U_SC_GPIO_CLK_EN                  SC_GPIO_CLK_EN                  ; /* 320 */
    volatile U_SC_GPIO_CLK_DIS                 SC_GPIO_CLK_DIS                 ; /* 324 */
    volatile U_SC_GIC_CLK_EN                   SC_GIC_CLK_EN                   ; /* 330 */
    volatile U_SC_GIC_CLK_DIS                  SC_GIC_CLK_DIS                  ; /* 334 */
    volatile U_SC_SMMU_ICG_EN                  SC_SMMU_ICG_EN                  ; /* 380 */
    volatile U_SC_SMMU_ICG_DIS                 SC_SMMU_ICG_DIS                 ; /* 384 */
    volatile U_SC_TIMER32_CLK_EN0              SC_TIMER32_CLK_EN0              ; /* 500 */
    volatile U_SC_TIMER32_CLK_DIS0             SC_TIMER32_CLK_DIS0             ; /* 504 */
    volatile U_SC_TIMER32_CLK_EN1              SC_TIMER32_CLK_EN1              ; /* 508 */
    volatile U_SC_TIMER32_CLK_DIS1             SC_TIMER32_CLK_DIS1             ; /* 50C */
    volatile U_SC_TIMER64_CLK_EN               SC_TIMER64_CLK_EN               ; /* 510 */
    volatile U_SC_TIMER64_CLK_DIS              SC_TIMER64_CLK_DIS              ; /* 514 */
    volatile U_SC_WATCHDOG_CLK_EN              SC_WATCHDOG_CLK_EN              ; /* 520 */
    volatile U_SC_WATCHDOG_CLK_DIS             SC_WATCHDOG_CLK_DIS             ; /* 524 */
    volatile U_SC_UART_CLK_EN                  SC_UART_CLK_EN                  ; /* 548 */
    volatile U_SC_UART_CLK_DIS                 SC_UART_CLK_DIS                 ; /* 54C */
    volatile U_SC_MDIO_CLK_EN                  SC_MDIO_CLK_EN                  ; /* 560 */
    volatile U_SC_MDIO_CLK_DIS                 SC_MDIO_CLK_DIS                 ; /* 564 */
    volatile U_SC_SMB_CLK_EN                   SC_SMB_CLK_EN                   ; /* 590 */
    volatile U_SC_SMB_CLK_DIS                  SC_SMB_CLK_DIS                  ; /* 594 */
    volatile U_SC_CER_CLK_EN                   SC_CER_CLK_EN                   ; /* 598 */
    volatile U_SC_CER_CLK_DIS                  SC_CER_CLK_DIS                  ; /* 59C */
    volatile U_SC_SFC2X_CLK_EN                 SC_SFC2X_CLK_EN                 ; /* 5A0 */
    volatile U_SC_SC2X_CLK_DIS                 SC_SC2X_CLK_DIS                 ; /* 5A4 */
    volatile U_SC_SFC1X_CLK_EN                 SC_SFC1X_CLK_EN                 ; /* 5A8 */
    volatile U_SC_SFC1X_CLK_DIS                SC_SFC1X_CLK_DIS                ; /* 5AC */
    volatile U_SC_SDMA_ICG_EN                  SC_SDMA_ICG_EN                  ; /* 5B0 */
    volatile U_SC_SDMA_ICG_DIS                 SC_SDMA_ICG_DIS                 ; /* 5B4 */
    volatile U_SC_TRNG_ICG_EN                  SC_TRNG_ICG_EN                  ; /* 5B8 */
    volatile U_SC_TRNG_ICG_DIS                 SC_TRNG_ICG_DIS                 ; /* 5BC */
    volatile U_SC_EMMC_ICG_EN                  SC_EMMC_ICG_EN                  ; /* 5C0 */
    volatile U_SC_EMMC_ICG_DIS                 SC_EMMC_ICG_DIS                 ; /* 5C4 */
    volatile U_SC_ITS_RESET_REQ                SC_ITS_RESET_REQ                ; /* A00 */
    volatile U_SC_ITS_RESET_DREQ               SC_ITS_RESET_DREQ               ; /* A04 */
    volatile U_SC_FTE_RESET_REQ                SC_FTE_RESET_REQ                ; /* A08 */
    volatile U_SC_FTE_RESET_DREQ               SC_FTE_RESET_DREQ               ; /* A0C */
    volatile U_SC_DBG_RESET_REQ                SC_DBG_RESET_REQ                ; /* A10 */
    volatile U_SC_DBG_RESET_DREQ               SC_DBG_RESET_DREQ               ; /* A14 */
    volatile U_SC_GPIO_RESET_REQ               SC_GPIO_RESET_REQ               ; /* A20 */
    volatile U_SC_GPIO_RESET_DREQ              SC_GPIO_RESET_DREQ              ; /* A24 */
    volatile U_SC_WATCHDOG_RESET_REQ           SC_WATCHDOG_RESET_REQ           ; /* C00 */
    volatile U_SC_WATCHDOG_RESET_DREQ          SC_WATCHDOG_RESET_DREQ          ; /* C04 */
    volatile U_SC_GIC_RESET_REQ                SC_GIC_RESET_REQ                ; /* C08 */
    volatile U_SC_GIC_RESET_DREQ               SC_GIC_RESET_DREQ               ; /* C0C */
    volatile U_SC_UART_RESET_REQ               SC_UART_RESET_REQ               ; /* C28 */
    volatile U_SC_UART_RESET_DREQ              SC_UART_RESET_DREQ              ; /* C2C */
    volatile U_SC_MDIO_RESET_REQ               SC_MDIO_RESET_REQ               ; /* C40 */
    volatile U_SC_MDIO_RESET_DREQ              SC_MDIO_RESET_DREQ              ; /* C44 */
    volatile U_SC_M3_RESET_REQ                 SC_M3_RESET_REQ                 ; /* C68 */
    volatile U_SC_M3_RESET_DREQ                SC_M3_RESET_DREQ                ; /* C6C */
    volatile U_SC_SMB_RESET_REQ                SC_SMB_RESET_REQ                ; /* C70 */
    volatile U_SC_SMB_RESET_DREQ               SC_SMB_RESET_DREQ               ; /* C74 */
    volatile U_SC_CER_RESET_REQ                SC_CER_RESET_REQ                ; /* C78 */
    volatile U_SC_CER_RESET_DREQ               SC_CER_RESET_DREQ               ; /* C7C */
    volatile U_SC_TIMER_RESET_REQ              SC_TIMER_RESET_REQ              ; /* C80 */
    volatile U_SC_TIMER_RESET_DREQ             SC_TIMER_RESET_DREQ             ; /* C84 */
    volatile U_SC_SFC_RESET_REQ                SC_SFC_RESET_REQ                ; /* C90 */
    volatile U_SC_SFC_RESET_DREQ               SC_SFC_RESET_DREQ               ; /* C94 */
    volatile U_SC_SDMA_RESET_REQ               SC_SDMA_RESET_REQ               ; /* CA0 */
    volatile U_SC_SDMA_RESET_DREQ              SC_SDMA_RESET_DREQ              ; /* CA4 */
    volatile U_SC_TRNG_RESET_REQ               SC_TRNG_RESET_REQ               ; /* CA8 */
    volatile U_SC_TRNG_RESET_DREQ              SC_TRNG_RESET_DREQ              ; /* CAC */
    volatile U_SC_EMMC_RESET_REQ               SC_EMMC_RESET_REQ               ; /* CB0 */
    volatile U_SC_EMMC_RESET_DREQ              SC_EMMC_RESET_DREQ              ; /* CB4 */
    volatile U_SC_CHAIN_ERR_CLR                SC_CHAIN_ERR_CLR                ; /* 1100 */
    volatile U_SC_CHAIN_ERR_INTMASK            SC_CHAIN_ERR_INTMASK            ; /* 1104 */
    volatile U_SC_CHAIN_ERR_INT_STATUS         SC_CHAIN_ERR_INT_STATUS         ; /* 1108 */
    volatile U_SC_CHAIN_ERR_CPU_CLR            SC_CHAIN_ERR_CPU_CLR            ; /* 1110 */
    volatile U_SC_CHAIN_ERR_CPU_INTMASK        SC_CHAIN_ERR_CPU_INTMASK        ; /* 1114 */
    volatile U_SC_CHAIN_ERR_CPU_INT_STATUS     SC_CHAIN_ERR_CPU_INT_STATUS     ; /* 1118 */
    volatile U_SC_DISPATCH_ERRRSP              SC_DISPATCH_ERRRSP              ; /* 2064 */
    volatile U_SC_M3_CTRL0                     SC_M3_CTRL0                     ; /* 20B0 */
    volatile U_SC_M3_CTRL1                     SC_M3_CTRL1                     ; /* 20B4 */
    volatile U_SC_TSENSOR1_ALARM0              SC_TSENSOR1_ALARM0              ; /* 20C0 */
    volatile U_SC_TSENSOR1_SAMPLE_NUM          SC_TSENSOR1_SAMPLE_NUM          ; /* 20C4 */
    volatile U_SC_TSENSOR1_CTRL                SC_TSENSOR1_CTRL                ; /* 20D0 */
    volatile U_SC_ULTRASOC_USER_CFG            SC_ULTRASOC_USER_CFG            ; /* 2100 */
    volatile U_SC_ULTRASOC_PORT_SEL            SC_ULTRASOC_PORT_SEL            ; /* 2104 */
    volatile U_SC_ULTRASOC_USER_NS_CFG         SC_ULTRASOC_USER_NS_CFG         ; /* 2108 */
    volatile U_SC_ULTRASOC_CTRL                SC_ULTRASOC_CTRL                ; /* 210C */
    volatile U_SC_M3_REMAP_ADDR_EN             SC_M3_REMAP_ADDR_EN             ; /* 2190 */
    volatile U_SC_M3_REMAP_ADDR_0              SC_M3_REMAP_ADDR_0              ; /* 2194 */
    volatile U_SC_M3_REMAP_ADDR_1              SC_M3_REMAP_ADDR_1              ; /* 2198 */
    volatile U_SC_M3_REMAP_ADDR_2              SC_M3_REMAP_ADDR_2              ; /* 219C */
    volatile U_SC_M3_REMAP_ADDR_3              SC_M3_REMAP_ADDR_3              ; /* 21A0 */
    volatile U_SC_M3_REMAP_ADDR_4              SC_M3_REMAP_ADDR_4              ; /* 21A4 */
    volatile U_SC_M3_REMAP_ADDR_5              SC_M3_REMAP_ADDR_5              ; /* 21A8 */
    volatile U_SC_M3_REMAP_ADDR_6              SC_M3_REMAP_ADDR_6              ; /* 21AC */
    volatile U_SC_M3_REMAP_ADDR_7              SC_M3_REMAP_ADDR_7              ; /* 21B0 */
    volatile U_SC_M3_REMAP_ADDR_8              SC_M3_REMAP_ADDR_8              ; /* 21B4 */
    volatile U_SC_M3_REMAP_ADDR_9              SC_M3_REMAP_ADDR_9              ; /* 21B8 */
    volatile U_SC_M3_REMAP_ADDR_10             SC_M3_REMAP_ADDR_10             ; /* 21BC */
    volatile U_SC_M3_REMAP_ADDR_11             SC_M3_REMAP_ADDR_11             ; /* 21C0 */
    volatile U_SC_M3_REMAP_ADDR_12             SC_M3_REMAP_ADDR_12             ; /* 21C4 */
    volatile U_SC_M3_REMAP_ADDR_13             SC_M3_REMAP_ADDR_13             ; /* 21C8 */
    volatile U_SC_M3_REMAP_ADDR_14             SC_M3_REMAP_ADDR_14             ; /* 21CC */
    volatile U_SC_M3_REMAP_ADDR_15             SC_M3_REMAP_ADDR_15             ; /* 21D0 */
    volatile U_SC_CFG_AXUSER_L_M3_0            SC_CFG_AXUSER_L_M3_0            ; /* 2208 */
    volatile U_SC_CFG_AXUSER_M_M3_0            SC_CFG_AXUSER_M_M3_0            ; /* 220C */
    volatile U_SC_CFG_AXUSER_H_M3_0            SC_CFG_AXUSER_H_M3_0            ; /* 2210 */
    volatile U_SC_CFG_CACHE_CTRL_M3_0          SC_CFG_CACHE_CTRL_M3_0          ; /* 2214 */
    volatile U_SC_CFG_AXUSER_L_M3_1            SC_CFG_AXUSER_L_M3_1            ; /* 2220 */
    volatile U_SC_CFG_AXUSER_M_M3_1            SC_CFG_AXUSER_M_M3_1            ; /* 2224 */
    volatile U_SC_CFG_AXUSER_H_M3_1            SC_CFG_AXUSER_H_M3_1            ; /* 2228 */
    volatile U_SC_CFG_CACHE_CTRL_M3_1          SC_CFG_CACHE_CTRL_M3_1          ; /* 222C */
    volatile U_SC_CFG_AXUSER_L_M3_2            SC_CFG_AXUSER_L_M3_2            ; /* 2230 */
    volatile U_SC_CFG_AXUSER_M_M3_2            SC_CFG_AXUSER_M_M3_2            ; /* 2234 */
    volatile U_SC_CFG_AXUSER_H_M3_2            SC_CFG_AXUSER_H_M3_2            ; /* 2238 */
    volatile U_SC_CFG_CACHE_CTRL_M3_2          SC_CFG_CACHE_CTRL_M3_2          ; /* 223C */
    volatile U_SC_QOS_CTRL_M3                  SC_QOS_CTRL_M3                  ; /* 2240 */
    volatile U_SC_QOS_CTRL_GIC                 SC_QOS_CTRL_GIC                 ; /* 2244 */
    volatile U_SC_QOS_CTRL_EMMC                SC_QOS_CTRL_EMMC                ; /* 2248 */
    volatile U_SC_QOS_CTRL_SDMAM               SC_QOS_CTRL_SDMAM               ; /* 224C */
    volatile U_SC_EXT_INT_POLARITY             SC_EXT_INT_POLARITY             ; /* 2300 */
    volatile U_SC_CFG_BUS_CTRL0                SC_CFG_BUS_CTRL0                ; /* 2400 */
    volatile U_SC_CFG_BUS_CTRL1                SC_CFG_BUS_CTRL1                ; /* 2404 */
    volatile U_SC_CFG_BUS_DBG_CTRL0            SC_CFG_BUS_DBG_CTRL0            ; /* 2408 */
    volatile U_SC_CFG_BUS_DBG_CTRL1            SC_CFG_BUS_DBG_CTRL1            ; /* 240C */
    volatile U_SC_MEM_CTRL_SMMU                SC_MEM_CTRL_SMMU                ; /* 3000 */
    volatile U_SC_MEM_CTRL_GIC                 SC_MEM_CTRL_GIC                 ; /* 3020 */
    volatile U_SC_MEM_CTRL_ULTRASOC            SC_MEM_CTRL_ULTRASOC            ; /* 3040 */
    volatile U_SC_MEM_CTRL_CER                 SC_MEM_CTRL_CER                 ; /* 3050 */
    volatile U_SC_MEM_CTRL_TRNG                SC_MEM_CTRL_TRNG                ; /* 3060 */
    volatile U_SC_TIMER64_EN_CTRL              SC_TIMER64_EN_CTRL              ; /* 3104 */
    volatile U_SC_WDOG_SRST_MASK               SC_WDOG_SRST_MASK               ; /* 3200 */
    volatile U_SC_TIMER_CLK_SEL                SC_TIMER_CLK_SEL                ; /* 3134 */
    volatile U_SC_BUS_NUM_PERI                 SC_BUS_NUM_PERI                 ; /* 3400 */
    volatile U_SC_DVE_NUM_PERI                 SC_DVE_NUM_PERI                 ; /* 3404 */
    volatile U_SC_CFG_BUS_WAIT                 SC_CFG_BUS_WAIT                 ; /* 3410 */
    volatile U_SC_EMMC_CLK_SEL                 SC_EMMC_CLK_SEL                 ; /* 3500 */
    volatile U_SC_AXI_USER_L32_EMMC            SC_AXI_USER_L32_EMMC            ; /* 3504 */
    volatile U_SC_AXI_USER_H32_EMMC            SC_AXI_USER_H32_EMMC            ; /* 3508 */
    volatile U_SC_AXI_USER_67_64_EMMC          SC_AXI_USER_67_64_EMMC          ; /* 350C */
    volatile U_SC_AXI_CACHE_EMMC               SC_AXI_CACHE_EMMC               ; /* 3510 */
    volatile U_SC_AXI_PORT_SEL                 SC_AXI_PORT_SEL                 ; /* 3514 */
    volatile U_SC_SFC_BYP_CTRL                 SC_SFC_BYP_CTRL                 ; /* 3518 */
    volatile U_SC_AHB_BYP_CTRL                 SC_AHB_BYP_CTRL                 ; /* 351C */
    volatile U_SC_UART_SEL                     SC_UART_SEL                     ; /* 3520 */
    volatile U_SC_ULTRASOC_USER_CRL            SC_ULTRASOC_USER_CRL            ; /* 3600 */
    volatile U_SC_ULTRASOC_AXPROT_CRL          SC_ULTRASOC_AXPROT_CRL          ; /* 3604 */
    volatile U_SC_SFC_DAW_CRL                  SC_SFC_DAW_CRL                  ; /* 3650 */
    volatile U_SC_EMMC_HADDR39_CRL             SC_EMMC_HADDR39_CRL             ; /* 3680 */
    volatile U_SC_EXT_INT_MASK                 SC_EXT_INT_MASK                 ; /* 3800 */
    volatile U_SC_AO_WAKEUP_INT_MASK           SC_AO_WAKEUP_INT_MASK           ; /* 3804 */
    volatile U_SC_TSENSOR1_INT                 SC_TSENSOR1_INT                 ; /* 4010 */
    volatile U_SC_TSENSOR1_INT_MASK            SC_TSENSOR1_INT_MASK            ; /* 4014 */
    volatile U_SC_PCIE_PERST_INT               SC_PCIE_PERST_INT               ; /* 4050 */
    volatile U_SC_PCIE_PERST_INT_MASK          SC_PCIE_PERST_INT_MASK          ; /* 4054 */
    volatile U_SC_PWR_CORE_INT                 SC_PWR_CORE_INT                 ; /* 4070 */
    volatile U_SC_PWR_CORE_INT_MASK            SC_PWR_CORE_INT_MASK            ; /* 4074 */
    volatile U_SC_ITS_CLK_ST                   SC_ITS_CLK_ST                   ; /* 5300 */
    volatile U_SC_FTE_CLK_ST                   SC_FTE_CLK_ST                   ; /* 5308 */
    volatile U_SC_DBG_CLK_ST                   SC_DBG_CLK_ST                   ; /* 5310 */
    volatile U_SC_M3_CLK_ST                    SC_M3_CLK_ST                    ; /* 5318 */
    volatile U_SC_GPIO_CLK_ST                  SC_GPIO_CLK_ST                  ; /* 5320 */
    volatile U_SC_GIC_CLK_ST                   SC_GIC_CLK_ST                   ; /* 5330 */
    volatile U_SC_SMMU_ICG_ST                  SC_SMMU_ICG_ST                  ; /* 5380 */
    volatile U_SC_TIMER32_CLK_ST0              SC_TIMER32_CLK_ST0              ; /* 5500 */
    volatile U_SC_TIMER32_CLK_ST1              SC_TIMER32_CLK_ST1              ; /* 5508 */
    volatile U_SC_TIMER64_CLK_ST               SC_TIMER64_CLK_ST               ; /* 5510 */
    volatile U_SC_WATCHDOG_CLK_ST              SC_WATCHDOG_CLK_ST              ; /* 5520 */
    volatile U_SC_UART_CLK_ST                  SC_UART_CLK_ST                  ; /* 5548 */
    volatile U_SC_MDIO_CLK_ST                  SC_MDIO_CLK_ST                  ; /* 5560 */
    volatile U_SC_SMB_CLK_ST                   SC_SMB_CLK_ST                   ; /* 5590 */
    volatile U_SC_CER_CLK_ST                   SC_CER_CLK_ST                   ; /* 5598 */
    volatile U_SC_SFC2X_CLK_ST                 SC_SFC2X_CLK_ST                 ; /* 55A0 */
    volatile U_SC_SFC1X_CLK_ST                 SC_SFC1X_CLK_ST                 ; /* 55A8 */
    volatile U_SC_SDMA_CLK_ST                  SC_SDMA_CLK_ST                  ; /* 55B0 */
    volatile U_SC_TRNG_CLK_ST                  SC_TRNG_CLK_ST                  ; /* 55B8 */
    volatile U_SC_EMMC_CLK_ST                  SC_EMMC_CLK_ST                  ; /* 55C0 */
    volatile U_SC_ITS_RESET_ST                 SC_ITS_RESET_ST                 ; /* 5A00 */
    volatile U_SC_FTE_RESET_ST                 SC_FTE_RESET_ST                 ; /* 5A08 */
    volatile U_SC_DBG_RESET_ST                 SC_DBG_RESET_ST                 ; /* 5A10 */
    volatile U_SC_GPIO_RESET_ST                SC_GPIO_RESET_ST                ; /* 5A20 */
    volatile U_SC_WATCHDOG_RESET_ST            SC_WATCHDOG_RESET_ST            ; /* 5C00 */
    volatile U_SC_GIC_RESET_ST                 SC_GIC_RESET_ST                 ; /* 5C08 */
    volatile U_SC_UART_RESET_ST                SC_UART_RESET_ST                ; /* 5C28 */
    volatile U_SC_MDIO_RESET_ST                SC_MDIO_RESET_ST                ; /* 5C40 */
    volatile U_SC_M3_RESET_ST                  SC_M3_RESET_ST                  ; /* 5C68 */
    volatile U_SC_SMB_RESET_ST                 SC_SMB_RESET_ST                 ; /* 5C70 */
    volatile U_SC_CER_RESET_ST                 SC_CER_RESET_ST                 ; /* 5C78 */
    volatile U_SC_TIMER_RESET_ST               SC_TIMER_RESET_ST               ; /* 5C80 */
    volatile U_SC_SFC_RESET_ST                 SC_SFC_RESET_ST                 ; /* 5C90 */
    volatile U_SC_SDMA_RESET_ST                SC_SDMA_RESET_ST                ; /* 5CA0 */
    volatile U_SC_TRNG_RESET_ST                SC_TRNG_RESET_ST                ; /* 5CA8 */
    volatile U_SC_EMMC_RESET_ST                SC_EMMC_RESET_ST                ; /* 5CB0 */
    volatile U_SC_TSENSOR1_ST                  SC_TSENSOR1_ST                  ; /* 60D0 */
    volatile U_SC_TSENSOR1_TEMP_SAMPLE_AVERAGE SC_TSENSOR1_TEMP_SAMPLE_AVERAGE ; /* 60D4 */
    volatile U_SC_ULTRASOC_MEM_ECC             SC_ULTRASOC_MEM_ECC             ; /* 6100 */
    volatile U_SC_M3_STAT                      SC_M3_STAT                      ; /* 6104 */
    volatile U_SC_PCIE_PERESET_ST              SC_PCIE_PERESET_ST              ; /* 6200 */
    volatile U_SC_EXT_INT_POLARITY_ST          SC_EXT_INT_POLARITY_ST          ; /* 6300 */
    volatile U_SC_EXT_INT_POLARITY_MASK_ST     SC_EXT_INT_POLARITY_MASK_ST     ; /* 6304 */
    volatile U_SC_TRNG_FSM_CTRL                SC_TRNG_FSM_CTRL                ; /* 8000 */
    volatile U_SC_TSENSOR1_INT_STATUS          SC_TSENSOR1_INT_STATUS          ; /* 8010 */
    volatile U_SC_PCIE_PERST_INT_STATUS        SC_PCIE_PERST_INT_STATUS        ; /* 8050 */
    volatile U_SC_PWR_CORE_INT_STATUS          SC_PWR_CORE_INT_STATUS          ; /* 8070 */
    volatile U_SC_KEY_INFO                     SC_KEY_INFO                     ; /* E000 */
    volatile U_PERI_CFG_VERSION0               PERI_CFG_VERSION0               ; /* E0A0 */
    volatile U_PERI_CFG_MAGIC_WORD             PERI_CFG_MAGIC_WORD             ; /* E0A4 */
    volatile U_PERI_CFG_ECO_CFG0               PERI_CFG_ECO_CFG0               ; /* E0A8 */
    volatile U_PERI_CFG_ECO_CFG1               PERI_CFG_ECO_CFG1               ; /* E0AC */
    volatile U_PERI_CFG_ECO_CFG2               PERI_CFG_ECO_CFG2               ; /* E0B0 */
    volatile U_PERI_CFG_ECO_CFG3               PERI_CFG_ECO_CFG3               ; /* E0B4 */
    volatile U_SC_SYSCTRL_LOCK                 SC_SYSCTRL_LOCK                 ; /* F100 */
    volatile U_SC_SYSCTRL_UNLOCK               SC_SYSCTRL_UNLOCK               ; /* F110 */
    volatile U_SC_ECO_RSV0                     SC_ECO_RSV0                     ; /* FF00 */
    volatile U_SC_ECO_RSV1                     SC_ECO_RSV1                     ; /* FF04 */
    volatile U_SC_ECO_RSV2                     SC_ECO_RSV2                     ; /* FF08 */
    volatile U_SC_ECO_RSV3                     SC_ECO_RSV3                     ; /* FF0C */
    volatile U_SC_ECO_RSV4                     SC_ECO_RSV4                     ; /* FF10 */
    volatile U_SC_ECO_RSV5                     SC_ECO_RSV5                     ; /* FF14 */
    volatile U_FPGA_VER                        FPGA_VER                        ; /* FFFC */

} S_peri_cfg_REGS_TYPE;

/* Declare the struct pointor of the module peri_cfg */
extern volatile S_peri_cfg_REGS_TYPE *gopperi_cfgAllReg;

/* Declare the functions that set the member value */
int iSetSC_ITS_CLK_EN_icg_en_its(unsigned int uicg_en_its);
int iSetSC_ITS_CLK_DIS_icg_dis_its(unsigned int uicg_dis_its);
int iSetSC_FTE_CLK_EN_icg_en_fte(unsigned int uicg_en_fte);
int iSetSC_FTE_CLK_DIS_icg_dis_fte(unsigned int uicg_dis_fte);
int iSetSC_DBG_CLK_EN_icg_en_dbg(unsigned int uicg_en_dbg);
int iSetSC_DBG_CLK_DIS_icg_dis_dbg(unsigned int uicg_dis_dbg);
int iSetSC_M3_CLK_EN_icg_en_m3(unsigned int uicg_en_m3);
int iSetSC_M3_CLK_DIS_icg_dis_m3(unsigned int uicg_dis_m3);
int iSetSC_GPIO_CLK_EN_icg_en_gpio(unsigned int uicg_en_gpio);
int iSetSC_GPIO_CLK_DIS_icg_dis_gpio(unsigned int uicg_dis_gpio);
int iSetSC_GIC_CLK_EN_icg_en_gic(unsigned int uicg_en_gic);
int iSetSC_GIC_CLK_DIS_icg_dis_gic(unsigned int uicg_dis_gic);
int iSetSC_SMMU_ICG_EN_icg_en_smmu_trans(unsigned int uicg_en_smmu_trans);
int iSetSC_SMMU_ICG_DIS_icg_dis_smmu_trans(unsigned int uicg_dis_smmu_trans);
int iSetSC_TIMER32_CLK_EN0_icg_en_timer0(unsigned int uicg_en_timer0);
int iSetSC_TIMER32_CLK_DIS0_icg_dis_timer0(unsigned int uicg_dis_timer0);
int iSetSC_TIMER32_CLK_EN1_icg_en_timer1(unsigned int uicg_en_timer1);
int iSetSC_TIMER32_CLK_DIS1_icg_dis_timer1(unsigned int uicg_dis_timer1);
int iSetSC_TIMER64_CLK_EN_icg_en_timer2(unsigned int uicg_en_timer2);
int iSetSC_TIMER64_CLK_DIS_icg_dis_timer2(unsigned int uicg_dis_timer2);
int iSetSC_WATCHDOG_CLK_EN_icg_en_wdog(unsigned int uicg_en_wdog);
int iSetSC_WATCHDOG_CLK_DIS_icg_dis_wdog(unsigned int uicg_dis_wdog);
int iSetSC_UART_CLK_EN_icg_en_uart(unsigned int uicg_en_uart);
int iSetSC_UART_CLK_DIS_icg_dis_uart(unsigned int uicg_dis_uart);
int iSetSC_MDIO_CLK_EN_icg_en_mdio(unsigned int uicg_en_mdio);
int iSetSC_MDIO_CLK_DIS_icg_dis_mdio(unsigned int uicg_dis_mdio);
int iSetSC_SMB_CLK_EN_icg_en_smb(unsigned int uicg_en_smb);
int iSetSC_SMB_CLK_DIS_icg_dis_smb(unsigned int uicg_dis_smb);
int iSetSC_CER_CLK_EN_icg_en_cer_s(unsigned int uicg_en_cer_s);
int iSetSC_CER_CLK_EN_icg_en_cer_m(unsigned int uicg_en_cer_m);
int iSetSC_CER_CLK_DIS_icg_dis_cer_s(unsigned int uicg_dis_cer_s);
int iSetSC_CER_CLK_DIS_icg_dis_cer_m(unsigned int uicg_dis_cer_m);
int iSetSC_SFC2X_CLK_EN_icg_en_sfc2x(unsigned int uicg_en_sfc2x);
int iSetSC_SC2X_CLK_DIS_icg_dis_sfc2x(unsigned int uicg_dis_sfc2x);
int iSetSC_SFC1X_CLK_EN_icg_en_sfc1x(unsigned int uicg_en_sfc1x);
int iSetSC_SFC1X_CLK_DIS_icg_dis_sfc1x(unsigned int uicg_dis_sfc1x);
int iSetSC_SDMA_ICG_EN_icg_en_sdma(unsigned int uicg_en_sdma);
int iSetSC_SDMA_ICG_DIS_icg_dis_sdma(unsigned int uicg_dis_sdma);
int iSetSC_TRNG_ICG_EN_icg_en_trng(unsigned int uicg_en_trng);
int iSetSC_TRNG_ICG_DIS_icg_dis_trng(unsigned int uicg_dis_trng);
int iSetSC_EMMC_ICG_EN_icg_en_emmc(unsigned int uicg_en_emmc);
int iSetSC_EMMC_ICG_DIS_icg_dis_emmc(unsigned int uicg_dis_emmc);
int iSetSC_ITS_RESET_REQ_srst_req_its(unsigned int usrst_req_its);
int iSetSC_ITS_RESET_DREQ_srst_dreq_its(unsigned int usrst_dreq_its);
int iSetSC_FTE_RESET_REQ_srst_req_fte(unsigned int usrst_req_fte);
int iSetSC_FTE_RESET_DREQ_srst_dreq_fte(unsigned int usrst_dreq_fte);
int iSetSC_DBG_RESET_REQ_srst_req_dbg(unsigned int usrst_req_dbg);
int iSetSC_DBG_RESET_DREQ_srst_dreq_dbg(unsigned int usrst_dreq_dbg);
int iSetSC_GPIO_RESET_REQ_srst_req_gpio(unsigned int usrst_req_gpio);
int iSetSC_GPIO_RESET_DREQ_srst_dreq_gpio(unsigned int usrst_dreq_gpio);
int iSetSC_WATCHDOG_RESET_REQ_srst_req_wdog(unsigned int usrst_req_wdog);
int iSetSC_WATCHDOG_RESET_DREQ_srst_dreq_wdog(unsigned int usrst_dreq_wdog);
int iSetSC_GIC_RESET_REQ_srst_req_gic(unsigned int usrst_req_gic);
int iSetSC_GIC_RESET_DREQ_srst_dreq_gic(unsigned int usrst_dreq_gic);
int iSetSC_UART_RESET_REQ_srst_req_uart(unsigned int usrst_req_uart);
int iSetSC_UART_RESET_DREQ_srst_dreq_uart(unsigned int usrst_dreq_uart);
int iSetSC_MDIO_RESET_REQ_srst_req_mdio(unsigned int usrst_req_mdio);
int iSetSC_MDIO_RESET_DREQ_srst_dreq_mdio(unsigned int usrst_dreq_mdio);
int iSetSC_M3_RESET_REQ_srst_req_m3_7(unsigned int usrst_req_m3_7);
int iSetSC_M3_RESET_REQ_srst_req_m3_6(unsigned int usrst_req_m3_6);
int iSetSC_M3_RESET_REQ_srst_req_m3_5(unsigned int usrst_req_m3_5);
int iSetSC_M3_RESET_REQ_srst_req_m3_4(unsigned int usrst_req_m3_4);
int iSetSC_M3_RESET_REQ_srst_req_m3_3(unsigned int usrst_req_m3_3);
int iSetSC_M3_RESET_REQ_srst_req_m3_2(unsigned int usrst_req_m3_2);
int iSetSC_M3_RESET_REQ_srst_req_m3_1(unsigned int usrst_req_m3_1);
int iSetSC_M3_RESET_REQ_srst_req_m3_0(unsigned int usrst_req_m3_0);
int iSetSC_M3_RESET_REQ_srst_req_m3_por7(unsigned int usrst_req_m3_por7);
int iSetSC_M3_RESET_REQ_srst_req_m3_por6(unsigned int usrst_req_m3_por6);
int iSetSC_M3_RESET_REQ_srst_req_m3_por5(unsigned int usrst_req_m3_por5);
int iSetSC_M3_RESET_REQ_srst_req_m3_por4(unsigned int usrst_req_m3_por4);
int iSetSC_M3_RESET_REQ_srst_req_m3_por3(unsigned int usrst_req_m3_por3);
int iSetSC_M3_RESET_REQ_srst_req_m3_por2(unsigned int usrst_req_m3_por2);
int iSetSC_M3_RESET_REQ_srst_req_m3_por1(unsigned int usrst_req_m3_por1);
int iSetSC_M3_RESET_REQ_srst_req_m3_por0(unsigned int usrst_req_m3_por0);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_7(unsigned int usrst_dreq_m3_7);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_6(unsigned int usrst_dreq_m3_6);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_5(unsigned int usrst_dreq_m3_5);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_4(unsigned int usrst_dreq_m3_4);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_3(unsigned int usrst_dreq_m3_3);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_2(unsigned int usrst_dreq_m3_2);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_1(unsigned int usrst_dreq_m3_1);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_0(unsigned int usrst_dreq_m3_0);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_por7(unsigned int usrst_dreq_m3_por7);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_por6(unsigned int usrst_dreq_m3_por6);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_por5(unsigned int usrst_dreq_m3_por5);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_por4(unsigned int usrst_dreq_m3_por4);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_por3(unsigned int usrst_dreq_m3_por3);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_por2(unsigned int usrst_dreq_m3_por2);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_por1(unsigned int usrst_dreq_m3_por1);
int iSetSC_M3_RESET_DREQ_srst_dreq_m3_por0(unsigned int usrst_dreq_m3_por0);
int iSetSC_SMB_RESET_REQ_srst_req_smb(unsigned int usrst_req_smb);
int iSetSC_SMB_RESET_DREQ_srst_dreq_smb(unsigned int usrst_dreq_smb);
int iSetSC_CER_RESET_REQ_srst_req_cer_s(unsigned int usrst_req_cer_s);
int iSetSC_CER_RESET_REQ_srst_req_cer_m(unsigned int usrst_req_cer_m);
int iSetSC_CER_RESET_DREQ_srst_dreq_cer_s(unsigned int usrst_dreq_cer_s);
int iSetSC_CER_RESET_DREQ_srst_dreq_cer_m(unsigned int usrst_dreq_cer_m);
int iSetSC_TIMER_RESET_REQ_srst_req_timer(unsigned int usrst_req_timer);
int iSetSC_TIMER_RESET_DREQ_srst_dreq_timer(unsigned int usrst_dreq_timer);
int iSetSC_SFC_RESET_REQ_srst_req_sfc_bus(unsigned int usrst_req_sfc_bus);
int iSetSC_SFC_RESET_REQ_srst_req_sfc2x(unsigned int usrst_req_sfc2x);
int iSetSC_SFC_RESET_REQ_srst_req_sfc1x(unsigned int usrst_req_sfc1x);
int iSetSC_SFC_RESET_DREQ_srst_dreq_sfc_bus(unsigned int usrst_dreq_sfc_bus);
int iSetSC_SFC_RESET_DREQ_srst_dreq_sfc2x(unsigned int usrst_dreq_sfc2x);
int iSetSC_SFC_RESET_DREQ_srst_dreq_sfc1x(unsigned int usrst_dreq_sfc1x);
int iSetSC_SDMA_RESET_REQ_srst_req_sdma(unsigned int usrst_req_sdma);
int iSetSC_SDMA_RESET_DREQ_srst_dreq_sdma(unsigned int usrst_dreq_sdma);
int iSetSC_TRNG_RESET_REQ_srst_req_trng(unsigned int usrst_req_trng);
int iSetSC_TRNG_RESET_DREQ_srst_dreq_trng(unsigned int usrst_dreq_trng);
int iSetSC_EMMC_RESET_REQ_srst_req_emmc(unsigned int usrst_req_emmc);
int iSetSC_EMMC_RESET_DREQ_srst_dreq_emmc(unsigned int usrst_dreq_emmc);
int iSetSC_CHAIN_ERR_CLR_chain_err_int(unsigned int uchain_err_int);
int iSetSC_CHAIN_ERR_INTMASK_chain_err_intmask(unsigned int uchain_err_intmask);
int iSetSC_CHAIN_ERR_INT_STATUS_chain_err_intstatus(unsigned int uchain_err_intstatus);
int iSetSC_CHAIN_ERR_CPU_CLR_chain_err_cpu_int(unsigned int uchain_err_cpu_int);
int iSetSC_CHAIN_ERR_CPU_INTMASK_chain_err_cpu_intmask(unsigned int uchain_err_cpu_intmask);
int iSetSC_CHAIN_ERR_CPU_INT_STATUS_chain_err_cpu_intstatus(unsigned int uchain_err_cpu_intstatus);
int iSetSC_DISPATCH_ERRRSP_errrsp_disable(unsigned int uerrrsp_disable);
int iSetSC_M3_CTRL0_m3_dbgen(unsigned int um3_dbgen);
int iSetSC_M3_CTRL0_m3_rxev(unsigned int um3_rxev);
int iSetSC_M3_CTRL0_m3_intnmi(unsigned int um3_intnmi);
int iSetSC_M3_CTRL0_m3_stcalib(unsigned int um3_stcalib);
int iSetSC_M3_CTRL1_m3_niden(unsigned int um3_niden);
int iSetSC_M3_CTRL1_m3_dapen(unsigned int um3_dapen);
int iSetSC_M3_CTRL1_m3_bootrom_addr(unsigned int um3_bootrom_addr);
int iSetSC_TSENSOR1_ALARM0_tsensor1_ultra_high(unsigned int utsensor1_ultra_high);
int iSetSC_TSENSOR1_ALARM0_tsensor1_high(unsigned int utsensor1_high);
int iSetSC_TSENSOR1_ALARM0_tsensor1_low(unsigned int utsensor1_low);
int iSetSC_TSENSOR1_SAMPLE_NUM_tsensor1_sample_shift_num(unsigned int utsensor1_sample_shift_num);
int iSetSC_TSENSOR1_CTRL_tsensor1_temp_ct_sel(unsigned int utsensor1_temp_ct_sel);
int iSetSC_TSENSOR1_CTRL_tsensor1_temp_calib(unsigned int utsensor1_temp_calib);
int iSetSC_TSENSOR1_CTRL_tsensor1_temp_en(unsigned int utsensor1_temp_en);
int iSetSC_ULTRASOC_USER_CFG_axi_user_ultrasoc(unsigned int uaxi_user_ultrasoc);
int iSetSC_ULTRASOC_PORT_SEL_ultrasoc_msg_sel(unsigned int uultrasoc_msg_sel);
int iSetSC_ULTRASOC_USER_NS_CFG_axi_user_ns_ultrasoc(unsigned int uaxi_user_ns_ultrasoc);
int iSetSC_ULTRASOC_CTRL_wtsel_etf(unsigned int uwtsel_etf);
int iSetSC_ULTRASOC_CTRL_rtsel_etf(unsigned int urtsel_etf);
int iSetSC_ULTRASOC_CTRL_ultrasoc_niden(unsigned int uultrasoc_niden);
int iSetSC_ULTRASOC_CTRL_ultrasoc_dbgen(unsigned int uultrasoc_dbgen);
int iSetSC_M3_REMAP_ADDR_EN_m3_remap_addr_en(unsigned int um3_remap_addr_en);
int iSetSC_M3_REMAP_ADDR_0_m3_remap_addr_0(unsigned int um3_remap_addr_0);
int iSetSC_M3_REMAP_ADDR_1_m3_remap_addr_1(unsigned int um3_remap_addr_1);
int iSetSC_M3_REMAP_ADDR_2_m3_remap_addr_2(unsigned int um3_remap_addr_2);
int iSetSC_M3_REMAP_ADDR_3_m3_remap_addr_3(unsigned int um3_remap_addr_3);
int iSetSC_M3_REMAP_ADDR_4_m3_remap_addr_4(unsigned int um3_remap_addr_4);
int iSetSC_M3_REMAP_ADDR_5_m3_remap_addr_5(unsigned int um3_remap_addr_5);
int iSetSC_M3_REMAP_ADDR_6_m3_remap_addr_6(unsigned int um3_remap_addr_6);
int iSetSC_M3_REMAP_ADDR_7_m3_remap_addr_7(unsigned int um3_remap_addr_7);
int iSetSC_M3_REMAP_ADDR_8_m3_remap_addr_8(unsigned int um3_remap_addr_8);
int iSetSC_M3_REMAP_ADDR_9_m3_remap_addr_9(unsigned int um3_remap_addr_9);
int iSetSC_M3_REMAP_ADDR_10_m3_remap_addr_10(unsigned int um3_remap_addr_10);
int iSetSC_M3_REMAP_ADDR_11_m3_remap_addr_11(unsigned int um3_remap_addr_11);
int iSetSC_M3_REMAP_ADDR_12_m3_remap_addr_12(unsigned int um3_remap_addr_12);
int iSetSC_M3_REMAP_ADDR_13_m3_remap_addr_13(unsigned int um3_remap_addr_13);
int iSetSC_M3_REMAP_ADDR_14_m3_remap_addr_14(unsigned int um3_remap_addr_14);
int iSetSC_M3_REMAP_ADDR_15_m3_remap_addr_15(unsigned int um3_remap_addr_15);
int iSetSC_CFG_AXUSER_L_M3_0_sc_cfg_axuser_l_m3_0(unsigned int usc_cfg_axuser_l_m3_0);
int iSetSC_CFG_AXUSER_M_M3_0_sc_cfg_axuser_m_m3_0(unsigned int usc_cfg_axuser_m_m3_0);
int iSetSC_CFG_AXUSER_H_M3_0_sc_cfg_axuser_h_m3_0(unsigned int usc_cfg_axuser_h_m3_0);
int iSetSC_CFG_CACHE_CTRL_M3_0_sc_cfg_axcache_m3_0(unsigned int usc_cfg_axcache_m3_0);
int iSetSC_CFG_AXUSER_L_M3_1_sc_cfg_axuser_l_m3_1(unsigned int usc_cfg_axuser_l_m3_1);
int iSetSC_CFG_AXUSER_M_M3_1_sc_cfg_axuser_m_m3_1(unsigned int usc_cfg_axuser_m_m3_1);
int iSetSC_CFG_AXUSER_H_M3_1_sc_cfg_axuser_h_m3_1(unsigned int usc_cfg_axuser_h_m3_1);
int iSetSC_CFG_CACHE_CTRL_M3_1_sc_cfg_axcache_m3_1(unsigned int usc_cfg_axcache_m3_1);
int iSetSC_CFG_AXUSER_L_M3_2_sc_cfg_axuser_l_m3_2(unsigned int usc_cfg_axuser_l_m3_2);
int iSetSC_CFG_AXUSER_M_M3_2_sc_cfg_axuser_m_m3_2(unsigned int usc_cfg_axuser_m_m3_2);
int iSetSC_CFG_AXUSER_H_M3_2_sc_cfg_axuser_h_m3_2(unsigned int usc_cfg_axuser_h_m3_2);
int iSetSC_CFG_CACHE_CTRL_M3_2_sc_cfg_axcache_m3_2(unsigned int usc_cfg_axcache_m3_2);
int iSetSC_QOS_CTRL_M3_sc_arqos_m3(unsigned int usc_arqos_m3);
int iSetSC_QOS_CTRL_M3_sc_awqos_m3(unsigned int usc_awqos_m3);
int iSetSC_QOS_CTRL_GIC_sc_arqos_gic(unsigned int usc_arqos_gic);
int iSetSC_QOS_CTRL_GIC_sc_awqos_gic(unsigned int usc_awqos_gic);
int iSetSC_QOS_CTRL_EMMC_sc_arqos_emmc(unsigned int usc_arqos_emmc);
int iSetSC_QOS_CTRL_EMMC_sc_awqos_emmc(unsigned int usc_awqos_emmc);
int iSetSC_QOS_CTRL_SDMAM_sc_arqos_sdmam(unsigned int usc_arqos_sdmam);
int iSetSC_QOS_CTRL_SDMAM_sc_awqos_sdmam(unsigned int usc_awqos_sdmam);
int iSetSC_EXT_INT_POLARITY_sc_m2_perst_int_polarity(unsigned int usc_m2_perst_int_polarity);
int iSetSC_EXT_INT_POLARITY_sc_ge_phy_int_polarity(unsigned int usc_ge_phy_int_polarity);
int iSetSC_EXT_INT_POLARITY_sc_gphy_int_polarity(unsigned int usc_gphy_int_polarity);
int iSetSC_EXT_INT_POLARITY_sc_pmu_int_polarity(unsigned int usc_pmu_int_polarity);
int iSetSC_EXT_INT_POLARITY_sc_ext_int_polarity(unsigned int usc_ext_int_polarity);
int iSetSC_CFG_BUS_CTRL0_sc_cmd_delay_en_cfgbus(unsigned int usc_cmd_delay_en_cfgbus);
int iSetSC_CFG_BUS_CTRL1_sc_counter_cmd_delay_cfgbus(unsigned int usc_counter_cmd_delay_cfgbus);
int iSetSC_CFG_BUS_DBG_CTRL0_sc_cmd_delay_en_cfgbus_dbg(unsigned int usc_cmd_delay_en_cfgbus_dbg);
int iSetSC_CFG_BUS_DBG_CTRL1_sc_counter_cmd_delay_cfgbus_dbg(unsigned int usc_counter_cmd_delay_cfgbus_dbg);
int iSetSC_MEM_CTRL_SMMU_mem_power_mode_smmu(unsigned int umem_power_mode_smmu);
int iSetSC_MEM_CTRL_SMMU_sp_ram_tmod_smmu(unsigned int usp_ram_tmod_smmu);
int iSetSC_MEM_CTRL_GIC_sp_ram_tmod_gic(unsigned int usp_ram_tmod_gic);
int iSetSC_MEM_CTRL_ULTRASOC_sp_ram_tmod_ultrasoc(unsigned int usp_ram_tmod_ultrasoc);
int iSetSC_MEM_CTRL_CER_mem_power_mode_cer(unsigned int umem_power_mode_cer);
int iSetSC_MEM_CTRL_CER_sp_ram_tmod_cer(unsigned int usp_ram_tmod_cer);
int iSetSC_MEM_CTRL_TRNG_mem_power_mode_trng(unsigned int umem_power_mode_trng);
int iSetSC_MEM_CTRL_TRNG_sp_ram_tmod_trng(unsigned int usp_ram_tmod_trng);
int iSetSC_TIMER64_EN_CTRL_timer64_en_externa(unsigned int utimer64_en_externa);
int iSetSC_WDOG_SRST_MASK_crg_srst_wdog_en(unsigned int ucrg_srst_wdog_en);
int iSetSC_TIMER_CLK_SEL_timer_clk_sel(unsigned int utimer_clk_sel);
int iSetSC_BUS_NUM_PERI_sc_bus_num(unsigned int usc_bus_num);
int iSetSC_DVE_NUM_PERI_sc_dev_num(unsigned int usc_dev_num);
int iSetSC_CFG_BUS_WAIT_rd_wait_cycle(unsigned int urd_wait_cycle);
int iSetSC_CFG_BUS_WAIT_rd_wait_cycle_cpu(unsigned int urd_wait_cycle_cpu);
int iSetSC_EMMC_CLK_SEL_emmc_clk_sel(unsigned int uemmc_clk_sel);
int iSetSC_AXI_USER_L32_EMMC_sc_axi_user_l32_emmc(unsigned int usc_axi_user_l32_emmc);
int iSetSC_AXI_USER_H32_EMMC_sc_axi_user_h32_emmc(unsigned int usc_axi_user_h32_emmc);
int iSetSC_AXI_USER_67_64_EMMC_sc_axi_user_h67_64_emmc(unsigned int usc_axi_user_h67_64_emmc);
int iSetSC_AXI_CACHE_EMMC_sc_axi_cache_emmc(unsigned int usc_axi_cache_emmc);
int iSetSC_AXI_PORT_SEL_sc_axi_port_sel(unsigned int usc_axi_port_sel);
int iSetSC_SFC_BYP_CTRL_sc_byp_en_sfc_mem(unsigned int usc_byp_en_sfc_mem);
int iSetSC_SFC_BYP_CTRL_sc_byp_en_sfc_reg(unsigned int usc_byp_en_sfc_reg);
int iSetSC_AHB_BYP_CTRL_sc_byp_en_smb(unsigned int usc_byp_en_smb);
int iSetSC_AHB_BYP_CTRL_sc_byp_en_cer(unsigned int usc_byp_en_cer);
int iSetSC_UART_SEL_sc_uart_sel(unsigned int usc_uart_sel);
int iSetSC_ULTRASOC_USER_CRL_sc_axqos_ultrasoc(unsigned int usc_axqos_ultrasoc);
int iSetSC_ULTRASOC_USER_CRL_sc_axcache_ultrasoc(unsigned int usc_axcache_ultrasoc);
int iSetSC_ULTRASOC_AXPROT_CRL_sc_arprot_ultrasoc(unsigned int usc_arprot_ultrasoc);
int iSetSC_ULTRASOC_AXPROT_CRL_sc_awprot_ultrasoc(unsigned int usc_awprot_ultrasoc);
int iSetSC_SFC_DAW_CRL_sc_daw_en(unsigned int usc_daw_en);
int iSetSC_SFC_DAW_CRL_sc_daw_size(unsigned int usc_daw_size);
int iSetSC_SFC_DAW_CRL_sc_daw_addr(unsigned int usc_daw_addr);
int iSetSC_EMMC_HADDR39_CRL_sc_ahb_haddr_39_emmc(unsigned int usc_ahb_haddr_39_emmc);
int iSetSC_EXT_INT_MASK_ext_int_mask(unsigned int uext_int_mask);
int iSetSC_AO_WAKEUP_INT_MASK_hipcie_int_mask(unsigned int uhipcie_int_mask);
int iSetSC_AO_WAKEUP_INT_MASK_timer64_int_mask(unsigned int utimer64_int_mask);
int iSetSC_AO_WAKEUP_INT_MASK_gpio0_int_mask(unsigned int ugpio0_int_mask);
int iSetSC_TSENSOR1_INT_tsensor1_ultra_over(unsigned int utsensor1_ultra_over);
int iSetSC_TSENSOR1_INT_tsensor1_over(unsigned int utsensor1_over);
int iSetSC_TSENSOR1_INT_tsensor1_under(unsigned int utsensor1_under);
int iSetSC_TSENSOR1_INT_MASK_tsensor1_ultra_over_int_mask(unsigned int utsensor1_ultra_over_int_mask);
int iSetSC_TSENSOR1_INT_MASK_tsensor1_over_int_mask(unsigned int utsensor1_over_int_mask);
int iSetSC_TSENSOR1_INT_MASK_tsensor1_under_int_mask(unsigned int utsensor1_under_int_mask);
int iSetSC_PCIE_PERST_INT_pcie_perst(unsigned int upcie_perst);
int iSetSC_PCIE_PERST_INT_MASK_pcie_perst_int_mask(unsigned int upcie_perst_int_mask);
int iSetSC_PWR_CORE_INT_pwr_core(unsigned int upwr_core);
int iSetSC_PWR_CORE_INT_MASK_pwr_core_int_mask(unsigned int upwr_core_int_mask);
int iSetSC_ITS_CLK_ST_icg_st_its(unsigned int uicg_st_its);
int iSetSC_FTE_CLK_ST_icg_st_fte(unsigned int uicg_st_fte);
int iSetSC_DBG_CLK_ST_icg_st_dbg(unsigned int uicg_st_dbg);
int iSetSC_M3_CLK_ST_icg_st_m3(unsigned int uicg_st_m3);
int iSetSC_GPIO_CLK_ST_icg_st_gpio(unsigned int uicg_st_gpio);
int iSetSC_GIC_CLK_ST_icg_st_gic(unsigned int uicg_st_gic);
int iSetSC_SMMU_ICG_ST_icg_st_smmu_trans(unsigned int uicg_st_smmu_trans);
int iSetSC_TIMER32_CLK_ST0_icg_st_timer0(unsigned int uicg_st_timer0);
int iSetSC_TIMER32_CLK_ST1_icg_st_timer1(unsigned int uicg_st_timer1);
int iSetSC_TIMER64_CLK_ST_icg_st_timer2(unsigned int uicg_st_timer2);
int iSetSC_WATCHDOG_CLK_ST_icg_st_wdog(unsigned int uicg_st_wdog);
int iSetSC_UART_CLK_ST_icg_st_uart(unsigned int uicg_st_uart);
int iSetSC_MDIO_CLK_ST_icg_st_mdio(unsigned int uicg_st_mdio);
int iSetSC_SMB_CLK_ST_icg_st_smb(unsigned int uicg_st_smb);
int iSetSC_CER_CLK_ST_icg_st_cer_s(unsigned int uicg_st_cer_s);
int iSetSC_CER_CLK_ST_icg_st_cer_m(unsigned int uicg_st_cer_m);
int iSetSC_SFC2X_CLK_ST_icg_st_sfc2x(unsigned int uicg_st_sfc2x);
int iSetSC_SFC1X_CLK_ST_icg_st_sfc1x(unsigned int uicg_st_sfc1x);
int iSetSC_SDMA_CLK_ST_icg_st_sdma(unsigned int uicg_st_sdma);
int iSetSC_TRNG_CLK_ST_icg_st_trng(unsigned int uicg_st_trng);
int iSetSC_EMMC_CLK_ST_icg_st_emmc(unsigned int uicg_st_emmc);
int iSetSC_ITS_RESET_ST_srst_st_its(unsigned int usrst_st_its);
int iSetSC_FTE_RESET_ST_srst_st_fte(unsigned int usrst_st_fte);
int iSetSC_DBG_RESET_ST_srst_st_dbg(unsigned int usrst_st_dbg);
int iSetSC_GPIO_RESET_ST_srst_st_gpio(unsigned int usrst_st_gpio);
int iSetSC_WATCHDOG_RESET_ST_srst_st_wdog(unsigned int usrst_st_wdog);
int iSetSC_GIC_RESET_ST_srst_st_gic(unsigned int usrst_st_gic);
int iSetSC_UART_RESET_ST_srst_st_uart(unsigned int usrst_st_uart);
int iSetSC_MDIO_RESET_ST_srst_st_mdio(unsigned int usrst_st_mdio);
int iSetSC_M3_RESET_ST_srst_st_m3_7(unsigned int usrst_st_m3_7);
int iSetSC_M3_RESET_ST_srst_st_m3_6(unsigned int usrst_st_m3_6);
int iSetSC_M3_RESET_ST_srst_st_m3_5(unsigned int usrst_st_m3_5);
int iSetSC_M3_RESET_ST_srst_st_m3_4(unsigned int usrst_st_m3_4);
int iSetSC_M3_RESET_ST_srst_st_m3_3(unsigned int usrst_st_m3_3);
int iSetSC_M3_RESET_ST_srst_st_m3_2(unsigned int usrst_st_m3_2);
int iSetSC_M3_RESET_ST_srst_st_m3_1(unsigned int usrst_st_m3_1);
int iSetSC_M3_RESET_ST_srst_st_m3_0(unsigned int usrst_st_m3_0);
int iSetSC_M3_RESET_ST_srst_st_m3_por7(unsigned int usrst_st_m3_por7);
int iSetSC_M3_RESET_ST_srst_st_m3_por6(unsigned int usrst_st_m3_por6);
int iSetSC_M3_RESET_ST_srst_st_m3_por5(unsigned int usrst_st_m3_por5);
int iSetSC_M3_RESET_ST_srst_st_m3_por4(unsigned int usrst_st_m3_por4);
int iSetSC_M3_RESET_ST_srst_st_m3_por3(unsigned int usrst_st_m3_por3);
int iSetSC_M3_RESET_ST_srst_st_m3_por2(unsigned int usrst_st_m3_por2);
int iSetSC_M3_RESET_ST_srst_st_m3_por1(unsigned int usrst_st_m3_por1);
int iSetSC_M3_RESET_ST_srst_st_m3_por0(unsigned int usrst_st_m3_por0);
int iSetSC_SMB_RESET_ST_srst_st_smb(unsigned int usrst_st_smb);
int iSetSC_CER_RESET_ST_srst_st_cer_s(unsigned int usrst_st_cer_s);
int iSetSC_CER_RESET_ST_srst_st_cer_m(unsigned int usrst_st_cer_m);
int iSetSC_TIMER_RESET_ST_srsr_st_timer(unsigned int usrsr_st_timer);
int iSetSC_SFC_RESET_ST_srst_st_sfc_bus(unsigned int usrst_st_sfc_bus);
int iSetSC_SFC_RESET_ST_srst_st_sfc2x(unsigned int usrst_st_sfc2x);
int iSetSC_SFC_RESET_ST_srst_st_sfc1x(unsigned int usrst_st_sfc1x);
int iSetSC_SDMA_RESET_ST_srst_st_sdma(unsigned int usrst_st_sdma);
int iSetSC_TRNG_RESET_ST_srst_st_trng(unsigned int usrst_st_trng);
int iSetSC_EMMC_RESET_ST_srst_st_emmc(unsigned int usrst_st_emmc);
int iSetSC_TSENSOR1_ST_tsensor1_temp_ready(unsigned int utsensor1_temp_ready);
int iSetSC_TSENSOR1_ST_tsensor1_temp_out(unsigned int utsensor1_temp_out);
int iSetSC_TSENSOR1_TEMP_SAMPLE_AVERAGE_tsensor1_valid(unsigned int utsensor1_valid);
int iSetSC_TSENSOR1_TEMP_SAMPLE_AVERAGE_tsensor1_sample(unsigned int utsensor1_sample);
int iSetSC_ULTRASOC_MEM_ECC_mem_ecc_status_ultrasoc(unsigned int umem_ecc_status_ultrasoc);
int iSetSC_M3_STAT_m3_currpri(unsigned int um3_currpri);
int iSetSC_M3_STAT_m3_sleeping(unsigned int um3_sleeping);
int iSetSC_M3_STAT_m3_lockup(unsigned int um3_lockup);
int iSetSC_M3_STAT_m3_halted(unsigned int um3_halted);
int iSetSC_PCIE_PERESET_ST_pcie_perst_status_soft(unsigned int upcie_perst_status_soft);
int iSetSC_EXT_INT_POLARITY_ST_ext_int_polarity_st(unsigned int uext_int_polarity_st);
int iSetSC_EXT_INT_POLARITY_MASK_ST_ext_int_polarity_mask_st(unsigned int uext_int_polarity_mask_st);
int iSetSC_TRNG_FSM_CTRL_trng_fsm_state(unsigned int utrng_fsm_state);
int iSetSC_TRNG_FSM_CTRL_trng_pproc_state(unsigned int utrng_pproc_state);
int iSetSC_TSENSOR1_INT_STATUS_tsensor1_ultra_over_int_status(unsigned int utsensor1_ultra_over_int_status);
int iSetSC_TSENSOR1_INT_STATUS_tsensor1_over_int_status(unsigned int utsensor1_over_int_status);
int iSetSC_TSENSOR1_INT_STATUS_tsensor1_under_int_status(unsigned int utsensor1_under_int_status);
int iSetSC_PCIE_PERST_INT_STATUS_pcie_perst_int_status(unsigned int upcie_perst_int_status);
int iSetSC_PWR_CORE_INT_STATUS_pwr_core_int_status(unsigned int upwr_core_int_status);
int iSetSC_KEY_INFO_tsc_sync(unsigned int utsc_sync);
int iSetSC_KEY_INFO_boot_sel1(unsigned int uboot_sel1);
int iSetSC_KEY_INFO_boot_sel0(unsigned int uboot_sel0);
int iSetSC_KEY_INFO_iodie_type(unsigned int uiodie_type);
int iSetSC_KEY_INFO_test_mode1(unsigned int utest_mode1);
int iSetSC_KEY_INFO_test_mode0(unsigned int utest_mode0);
int iSetSC_KEY_INFO_mpcore_sel(unsigned int umpcore_sel);
int iSetSC_KEY_INFO_rst_mode(unsigned int urst_mode);
int iSetSC_KEY_INFO_probe_mode(unsigned int uprobe_mode);
int iSetSC_KEY_INFO_die_id(unsigned int udie_id);
int iSetSC_KEY_INFO_socket_id(unsigned int usocket_id);
int iSetPERI_CFG_VERSION0_peri_cfg_version0(unsigned int uperi_cfg_version0);
int iSetPERI_CFG_MAGIC_WORD_peri_cfg_magic_word(unsigned int uperi_cfg_magic_word);
int iSetPERI_CFG_ECO_CFG0_peri_cfg_eco_cfg0(unsigned int uperi_cfg_eco_cfg0);
int iSetPERI_CFG_ECO_CFG1_peri_cfg_eco_cfg1(unsigned int uperi_cfg_eco_cfg1);
int iSetPERI_CFG_ECO_CFG2_peri_cfg_eco_cfg2(unsigned int uperi_cfg_eco_cfg2);
int iSetPERI_CFG_ECO_CFG3_peri_cfg_eco_cfg3(unsigned int uperi_cfg_eco_cfg3);
int iSetSC_SYSCTRL_LOCK_sysctrl_lock(unsigned int usysctrl_lock);
int iSetSC_SYSCTRL_UNLOCK_sysctrl_unlock(unsigned int usysctrl_unlock);
int iSetSC_ECO_RSV0_eco_rsv0(unsigned int ueco_rsv0);
int iSetSC_ECO_RSV1_eco_rsv1(unsigned int ueco_rsv1);
int iSetSC_ECO_RSV2_eco_rsv2(unsigned int ueco_rsv2);
int iSetSC_ECO_RSV3_eco_rsv3(unsigned int ueco_rsv3);
int iSetSC_ECO_RSV4_prototype_clk(unsigned int uprototype_clk);
int iSetSC_ECO_RSV5_prototype_rst_n(unsigned int uprototype_rst_n);
int iSetFPGA_VER_fpga_veri_num(unsigned int ufpga_veri_num);

#endif // __PERI_CFG_C_UNION_DEFINE_H__
